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From: Paul Burton <paulburton@kernel.org>
To: Zhou Yanjie <zhouyanjie@zoho.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	ralf@linux-mips.org, jhogan@kernel.org,
	gregkh@linuxfoundation.org, paul.burton@mips.com,
	chenhc@lemote.com, paul@crapouillou.net, tglx@linutronix.de,
	jiaxun.yang@flygoat.com
Subject: Re: [PATCH 2/2] MIPS: Ingenic: Disable abandoned HPTLB function.
Date: Fri, 15 Nov 2019 13:37:16 -0800	[thread overview]
Message-ID: <20191115213716.wt4wn2moj3fup4dc@lantea.localdomain> (raw)
In-Reply-To: <1571909341-10108-3-git-send-email-zhouyanjie@zoho.com>

Hi Zhou,

On Thu, Oct 24, 2019 at 05:29:01PM +0800, Zhou Yanjie wrote:
> JZ4760/JZ4770/JZ4775/X1000/X1500 has an abandoned huge page
> tlb, write 0xa9000000 to cp0 config5 sel4 to disable this
> function to prevent getting stuck.

Can you describe how we "get stuck"? What actually goes wrong on the
affected CPUs? Do they misinterpret EntryLo values? Which bits do they
misinterpret?

> Confirmed by Ingenic,
> this operation will not adversely affect processors
> without HPTLB function.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  arch/mips/kernel/cpu-probe.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 16033a4..cfebf8c 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1966,11 +1966,23 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
>  	}
>  
>  	/*
> -	 * The config0 register in the Xburst CPUs with a processor ID of
> +	 * The config0 register in the XBurst CPUs with a processor ID of
> +	 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb, write
> +	 * 0xa9000000 to cp0 config5 sel4 to disable this function to

Saying "config5" suggests $16 sel 5 to me - Config5 is after all an
architecturally defined register & it's not this one. It'd be better to
say "cop0 register 5 sel 4".

> +	 * prevent getting stuck.
> +	 */
> +	if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D1) {
> +		__asm__ (
> +			"li    $2, 0xa9000000 \n\t"
> +			"mtc0  $2, $5, 4      \n\t"
> +			"nop                  \n\t"
> +			::"r"(2));

I'd prefer that you add #defines to asm/mipsregs.h to provide a
write_c0_X() function where X is replaced with whatever the name of this
register is, and preferably also #define macros describing the fields
present in the register. Writing a magic number isn't ideal.

> +	/*
> +	 * The config0 register in the XBurst CPUs with a processor ID of
>  	 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
>  	 * but they don't actually support this ISA.
>  	 */
> -	if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
> +	} else if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)

It might be cleaner to use a switch statement rather than writing out
the & PRID_COMP_MASK condition twice?

Thanks,
    Paul

  reply	other threads:[~2019-11-15 21:36 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24  9:28 Zhou Yanjie
2019-10-24  9:29 ` [PATCH 1/2] MIPS: Rename JZRISC to XBurst Zhou Yanjie
2019-10-24  9:29 ` [PATCH 2/2] MIPS: Ingenic: Disable abandoned HPTLB function Zhou Yanjie
2019-11-15 21:37   ` Paul Burton [this message]
2019-11-16 10:11     ` Zhou Yanjie
2019-11-17 11:49       ` Paul Cercueil
2019-11-17 16:36         ` Zhou Yanjie
2019-11-18  4:17         ` Zhou Yanjie
2019-11-15 18:49 ` Paul Cercueil
2019-11-16 17:23 ` MIPS: Ingenic: Disable abandoned HPTLB function v2 Zhou Yanjie
2019-11-16 17:23   ` [PATCH 1/2 v2] MIPS: Rename JZRISC to XBurst Zhou Yanjie
2019-11-16 17:23   ` [PATCH 2/2 v2] MIPS: Ingenic: Disable abandoned HPTLB function Zhou Yanjie
2019-11-19 14:28 ` MIPS: Ingenic: Disable abandoned HPTLB function v3 Zhou Yanjie
2019-11-19 14:28   ` [PATCH 1/2 v3] MIPS: Rename JZRISC to XBurst Zhou Yanjie
2019-11-19 14:28   ` [PATCH 2/2 v3] MIPS: Ingenic: Disable abandoned HPTLB function Zhou Yanjie
2019-11-20 11:45     ` Paul Cercueil
2019-11-22 22:06     ` Paul Burton

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