From: Stephen Boyd <sboyd@kernel.org>
To: "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>,
Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@intel.com>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
robhkernel.org@smile.fi.intel.com,
Mark Rutland <mark.rutland@arm.com>,
linux-clk <linux-clk@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
qi-ming.wu@intel.com, yixin.zhu@linux.intel.com,
cheol.yong.kim@intel.com, rahul.tanwar@intel.com
Subject: Re: [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC
Date: Mon, 23 Dec 2019 19:04:31 -0800 [thread overview]
Message-ID: <20191224030431.E0E93206B7@mail.kernel.org> (raw)
In-Reply-To: <CAHp75VdtsXjW5kaWVspi-5u6ya5512Yk7VN4HJ4Tn34PWci5Og@mail.gmail.com>
Quoting Andy Shevchenko (2019-12-07 06:57:43)
> On Fri, Dec 6, 2019 at 7:06 AM Tanwar, Rahul
> <rahul.tanwar@linux.intel.com> wrote:
> > On 2/9/2019 8:24 PM, Andy Shevchenko wrote:
> > >>
> > >> div = val < 3 ? (val + 1) : (1 << ((val - 3) / 3));
> > > It's not complete, but I think you got the idea.
> > >
> > >> So, can we eliminate table?
> >
> > In the desperation to eliminate table, below is what i can come up with:
> >
> > struct clk_div_table div_table[16];
>
> But this is not an elimination, it's just a replacement from static to
> dynamically calculated one.
>
> > int i, j;
> >
> > for (i = 0; i < 16; i++)
> > div_table[i].val = i;
> >
> > for (i = 0, j=0; i < 16; i+=3, j++) {
> > div_table[i].div = (i == 0) ? (1 << j) : (1 << (j + 1));
> > if (i == 15)
> > break;
> >
> > div_table[i + 1].div = (i == 0) ? ((1 << j) + 1) :
> > (1 << (j + 1)) + (1 << (j - 1));
> > div_table[i + 2].div = (3 << j);
> > }
> >
> > To me, table still looks a better approach. Also, table is more extendable &
> > consistent w.r.t. clk framework & other referenced clk drivers.
> >
> > Whats your opinion ?
>
> Whatever CCF maintainers is fine with.
>
Table is fine. Or something that calculates is also fine. Is it going to
be extended in the future? If we're talking about a driver for hardware
I wonder if this is really going to change in the future.
Please resend so your binding can be reviewed.
next prev parent reply other threads:[~2019-12-24 3:04 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 7:00 [PATCH v1 0/2] clk: intel: Add a new driver for a new clock controller IP Rahul Tanwar
2019-08-28 7:00 ` [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC Rahul Tanwar
2019-08-28 15:09 ` Andy Shevchenko
2019-09-02 7:43 ` Tanwar, Rahul
2019-09-02 12:20 ` Andy Shevchenko
2019-09-02 12:24 ` Andy Shevchenko
2019-12-06 4:39 ` Tanwar, Rahul
2019-12-07 14:57 ` Andy Shevchenko
2019-12-24 3:04 ` Stephen Boyd [this message]
2019-09-02 22:20 ` Martin Blumenstingl
2019-09-03 9:54 ` Tanwar, Rahul
2019-09-03 18:53 ` Martin Blumenstingl
2019-09-04 8:03 ` Tanwar, Rahul
2019-09-05 20:47 ` Martin Blumenstingl
2019-09-09 14:16 ` Kim, Cheol Yong
2019-09-16 18:36 ` Stephen Boyd
2019-09-03 23:54 ` Stephen Boyd
2019-08-28 7:00 ` [PATCH v1 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU Rahul Tanwar
2019-12-19 16:33 ` Rob Herring
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