* [PATCH 1/3] clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
2019-12-29 2:59 [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Samuel Holland
@ 2019-12-29 2:59 ` Samuel Holland
2019-12-29 2:59 ` [PATCH 2/3] clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition Samuel Holland
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Samuel Holland @ 2019-12-29 2:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi, Samuel Holland
According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 21 +++------------------
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 4646fdc61053..4c8c491b87c2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -51,19 +51,7 @@ static struct ccu_div ar100_clk = {
static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
-static struct ccu_div apb0_clk = {
- .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
-
- .common = {
- .reg = 0x0c,
- .hw.init = CLK_HW_INIT_HW("apb0",
- &ahb0_clk.hw,
- &ccu_div_ops,
- 0),
- },
-};
-
-static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
+static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
/*
* Define the parent as an array that can be reused to save space
@@ -127,7 +115,7 @@ static struct ccu_mp a83t_ir_clk = {
static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
&ar100_clk.common,
- &a83t_apb0_clk.common,
+ &apb0_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
&apb0_timer_clk.common,
@@ -167,7 +155,7 @@ static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
- [CLK_APB0] = &a83t_apb0_clk.common.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
@@ -282,9 +270,6 @@ static void __init sunxi_r_ccu_init(struct device_node *node,
static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
{
- /* Fix apb0 bus gate parents here */
- apb0_gate_parent[0] = &a83t_apb0_clk.common.hw;
-
sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
}
CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
--
2.23.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
2019-12-29 2:59 [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Samuel Holland
2019-12-29 2:59 ` [PATCH 1/3] clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock Samuel Holland
@ 2019-12-29 2:59 ` Samuel Holland
2019-12-29 2:59 ` [PATCH 3/3] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order Samuel Holland
2020-01-02 9:28 ` [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Samuel Holland @ 2019-12-29 2:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi, Samuel Holland
Like the APB0 clock on previous chips, this is a simple single-parent
clock with an M divider. Use the equivalent helper macro instead of
writing out the whole clock description manually.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 45a1ed3fe674..df9c01831699 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = {
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
-static struct ccu_div r_apb1_clk = {
- .div = _SUNXI_CCU_DIV(0, 2),
-
- .common = {
- .reg = 0x00c,
- .hw.init = CLK_HW_INIT("r-apb1",
- "r-ahb",
- &ccu_div_ops,
- 0),
- },
-};
+static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
--
2.23.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order
2019-12-29 2:59 [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Samuel Holland
2019-12-29 2:59 ` [PATCH 1/3] clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock Samuel Holland
2019-12-29 2:59 ` [PATCH 2/3] clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition Samuel Holland
@ 2019-12-29 2:59 ` Samuel Holland
2020-01-02 9:28 ` [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Samuel Holland @ 2019-12-29 2:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi, Samuel Holland
According to the BSP source code, both the AR100 and R_APB2 clocks have
PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre-
divider used for PLL_PERIPH0 should be changed to index 3 to match.
This was verified by running a rough benchmark on the AR100 with various
clock settings:
| mux | pre-divider | iterations/second | clock source |
|=====|=============|===================|==============|
| 0 | 0 | 19033 (stable) | osc24M |
| 2 | 5 | 11466 (unstable) | iosc/osc16M |
| 2 | 17 | 11422 (unstable) | iosc/osc16M |
| 3 | 5 | 85338 (stable) | pll-periph0 |
| 3 | 17 | 27167 (stable) | pll-periph0 |
The relative performance numbers all match up (with pll-periph0 running
at its default 600MHz).
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index df9c01831699..50f8d1bc7046 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -23,9 +23,9 @@
*/
static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
- "pll-periph0", "iosc" };
+ "iosc", "pll-periph0" };
static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
- { .index = 2, .shift = 0, .width = 5 },
+ { .index = 3, .shift = 0, .width = 5 },
};
static struct ccu_div ar100_clk = {
--
2.23.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] A64/H3/H6 R_CCU clock fixes
2019-12-29 2:59 [PATCH 0/3] A64/H3/H6 R_CCU clock fixes Samuel Holland
` (2 preceding siblings ...)
2019-12-29 2:59 ` [PATCH 3/3] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order Samuel Holland
@ 2020-01-02 9:28 ` Maxime Ripard
3 siblings, 0 replies; 5+ messages in thread
From: Maxime Ripard @ 2020-01-02 9:28 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, linux-sunxi
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On Sat, Dec 28, 2019 at 08:59:19PM -0600, Samuel Holland wrote:
> Hi all,
>
> I was examining the H6 BSP clock driver[1] for guidance when porting an
> AR100 firmware[2] to the H6 SoC. I found some inconsistencies between
> that code and the sunxi-ng driver.
>
> I don't have a good way to verify the first patch. Someone with an
> oscilloscope could set the divider and check the I2C/RSB frequency.
>
> Patch 2 should have no functional change.
>
> Patch 3 was verified by benchmarking. Details are in the commit message.
Applied all three, thanks
Maxime
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^ permalink raw reply [flat|nested] 5+ messages in thread