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From: James Morse <james.morse@arm.com>
To: x86@kernel.org, linux-kernel@vger.kernel.org
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	Reinette Chatre <reinette.chatre@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Babu Moger <Babu.Moger@amd.com>,
	James Morse <james.morse@arm.com>
Subject: [PATCH 08/10] x86/resctrl: Merge AMD/Intel parse_bw() calls
Date: Fri, 14 Feb 2020 18:23:59 +0000	[thread overview]
Message-ID: <20200214182401.39008-9-james.morse@arm.com> (raw)
In-Reply-To: <20200214182401.39008-1-james.morse@arm.com>

Now that we've explained arch_needs_linear to resctrl, the parse_bw()
calls are almost the same between AMD and Intel.

The difference is '!is_mba_sc()', which is not checked on AMD. This
will always be true on AMD CPUs as mba_sc cannot be enabled as
is_mba_linear() is false.

Removing this duplication means user-space visible behaviour and
error messages are not validated or generated in different places.

Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/x86/kernel/cpu/resctrl/core.c        |  4 +-
 arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 55 +----------------------
 arch/x86/kernel/cpu/resctrl/internal.h    |  6 +--
 3 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index f022dc823c53..e90c10ca85f4 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -924,7 +924,7 @@ static __init void rdt_init_res_defs_intel(void)
 		else if (r->rid == RDT_RESOURCE_MBA) {
 			r->msr_base = MSR_IA32_MBA_THRTL_BASE;
 			r->msr_update = mba_wrmsr_intel;
-			r->parse_ctrlval = parse_bw_intel;
+			r->parse_ctrlval = parse_bw;
 		}
 	}
 }
@@ -944,7 +944,7 @@ static __init void rdt_init_res_defs_amd(void)
 		else if (r->rid == RDT_RESOURCE_MBA) {
 			r->msr_base = MSR_IA32_MBA_BW_BASE;
 			r->msr_update = mba_wrmsr_amd;
-			r->parse_ctrlval = parse_bw_amd;
+			r->parse_ctrlval = parse_bw;
 		}
 	}
 }
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index db8e6c0cadb1..416becb591d1 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -21,59 +21,6 @@
 #include <linux/slab.h>
 #include "internal.h"
 
-/*
- * Check whether MBA bandwidth percentage value is correct. The value is
- * checked against the minimum and maximum bandwidth values specified by
- * the hardware. The allocated bandwidth percentage is rounded to the next
- * control step available on the hardware.
- */
-static bool bw_validate_amd(char *buf, unsigned long *data,
-			    struct rdt_resource *r)
-{
-	unsigned long bw;
-	int ret;
-
-	/* temporary: always false on AMD */
-	if (!r->membw.delay_linear && r->membw.arch_needs_linear) {
-		rdt_last_cmd_puts("No support for non-linear MB domains\n");
-		return false;
-	}
-
-	ret = kstrtoul(buf, 10, &bw);
-	if (ret) {
-		rdt_last_cmd_printf("Non-decimal digit in MB value %s\n", buf);
-		return false;
-	}
-
-	if (bw < r->membw.min_bw || bw > r->default_ctrl) {
-		rdt_last_cmd_printf("MB value %ld out of range [%d,%d]\n", bw,
-				    r->membw.min_bw, r->default_ctrl);
-		return false;
-	}
-
-	*data = roundup(bw, (unsigned long)r->membw.bw_gran);
-	return true;
-}
-
-int parse_bw_amd(struct rdt_parse_data *data, struct rdt_resource *r,
-		 struct rdt_domain *d)
-{
-	unsigned long bw_val;
-
-	if (d->have_new_ctrl) {
-		rdt_last_cmd_printf("Duplicate domain %d\n", d->id);
-		return -EINVAL;
-	}
-
-	if (!bw_validate_amd(data->buf, &bw_val, r))
-		return -EINVAL;
-
-	d->new_ctrl = bw_val;
-	d->have_new_ctrl = true;
-
-	return 0;
-}
-
 /*
  * Check whether MBA bandwidth percentage value is correct. The value is
  * checked against the minimum and max bandwidth values specified by the
@@ -110,7 +57,7 @@ static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r)
 	return true;
 }
 
-int parse_bw_intel(struct rdt_parse_data *data, struct rdt_resource *r,
+int parse_bw(struct rdt_parse_data *data, struct rdt_resource *r,
 		   struct rdt_domain *d)
 {
 	unsigned long bw_val;
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 1fa692c54e15..45fc695081d1 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -462,10 +462,8 @@ struct rdt_resource {
 
 int parse_cbm(struct rdt_parse_data *data, struct rdt_resource *r,
 	      struct rdt_domain *d);
-int parse_bw_intel(struct rdt_parse_data *data, struct rdt_resource *r,
-		   struct rdt_domain *d);
-int parse_bw_amd(struct rdt_parse_data *data, struct rdt_resource *r,
-		 struct rdt_domain *d);
+int parse_bw(struct rdt_parse_data *data, struct rdt_resource *r,
+	     struct rdt_domain *d);
 
 extern struct mutex rdtgroup_mutex;
 
-- 
2.24.1


  parent reply	other threads:[~2020-02-14 18:25 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 18:23 [PATCH 00/10] x86/resctrl: Misc cleanup James Morse
2020-02-14 18:23 ` [PATCH 01/10] x86/resctrl: Nothing uses struct mbm_state chunks_bw James Morse
2020-03-16 18:09   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 02/10] x86/resctrl: Remove max_delay James Morse
2020-03-16 18:11   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 03/10] x86/resctrl: Fix stale comment James Morse
2020-03-16 18:12   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 04/10] x86/resctrl: use container_of() in delayed_work handlers James Morse
2020-03-16 18:13   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 05/10] x86/resctrl: Include pid.h James Morse
2020-03-16 18:13   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 06/10] x86/resctrl: Use is_closid_match() in more places James Morse
2020-03-16 18:15   ` Reinette Chatre
2020-02-14 18:23 ` [PATCH 07/10] x86/resctrl: Add arch_needs_linear to explain AMD/Intel MBA difference James Morse
2020-03-16 18:37   ` Reinette Chatre
2020-02-14 18:23 ` James Morse [this message]
2020-03-16 18:42   ` [PATCH 08/10] x86/resctrl: Merge AMD/Intel parse_bw() calls Reinette Chatre
2020-02-14 18:24 ` [PATCH 09/10] x86/resctrl: Add arch_has_sparse_bitmaps to explain AMD/Intel CAT difference James Morse
2020-03-16 18:58   ` Reinette Chatre
2020-02-14 18:24 ` [PATCH 10/10] cacheinfo: Move resctrl's get_cache_id() to the cacheinfo header file James Morse
2020-03-16 20:31   ` Reinette Chatre

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