* [PATCH 1/3] perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag
@ 2020-02-19 23:27 Kim Phillips
2020-02-19 23:27 ` [PATCH 2/3] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support Kim Phillips
2020-02-19 23:27 ` [PATCH 3/3] perf/amd/uncore: Add support for Family 19h L3 PMU Kim Phillips
0 siblings, 2 replies; 3+ messages in thread
From: Kim Phillips @ 2020-02-19 23:27 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Ingo Molnar
Cc: Kim Phillips, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Jiri Olsa, Mark Rutland,
Michael Petlan, Namhyung Kim, Thomas Gleixner, linux-kernel, x86,
stable
This enables the sampling check in kernel/events/core.c's
perf_event_open, which returns the more appropriate -EOPNOTSUPP.
BEFORE:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (l3_request_g1.caching_l3_cache_accesses).
/bin/dmesg | grep -i perf may provide additional information.
With nothing relevant in dmesg.
AFTER:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
l3_request_g1.caching_l3_cache_accesses: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: x86@kernel.org
Cc: stable@vger.kernel.org
Fixes: c43ca5091a37 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters")
---
arch/x86/events/amd/uncore.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index a6ea07f2aa84..4d867a752f0e 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -190,15 +190,12 @@ static int amd_uncore_event_init(struct perf_event *event)
/*
* NB and Last level cache counters (MSRs) are shared across all cores
- * that share the same NB / Last level cache. Interrupts can be directed
- * to a single target core, however, event counts generated by processes
- * running on other cores cannot be masked out. So we do not support
- * sampling and per-thread events.
+ * that share the same NB / Last level cache. On family 16h and below,
+ * Interrupts can be directed to a single target core, however, event
+ * counts generated by processes running on other cores cannot be masked
+ * out. So we do not support sampling and per-thread events via
+ * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
*/
- if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
- return -EINVAL;
-
- /* and we do not enable counter overflow interrupts */
hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
hwc->idx = -1;
@@ -306,7 +303,7 @@ static struct pmu amd_nb_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct pmu amd_llc_pmu = {
@@ -317,7 +314,7 @@ static struct pmu amd_llc_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
--
2.25.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/3] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support
2020-02-19 23:27 [PATCH 1/3] perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag Kim Phillips
@ 2020-02-19 23:27 ` Kim Phillips
2020-02-19 23:27 ` [PATCH 3/3] perf/amd/uncore: Add support for Family 19h L3 PMU Kim Phillips
1 sibling, 0 replies; 3+ messages in thread
From: Kim Phillips @ 2020-02-19 23:27 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Ingo Molnar
Cc: Kim Phillips, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Jiri Olsa, Mark Rutland,
Michael Petlan, Namhyung Kim, Thomas Gleixner, linux-kernel, x86
In order to better accommodate the upcoming Family 19h support,
given the 80-char line limit, we move the existing code into a new
l3_thread_slice_mask function, and convert it to use the more
readable topology_* helper functions.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: x86@kernel.org
---
arch/x86/events/amd/uncore.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 4d867a752f0e..e635c40ca9c4 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -180,6 +180,23 @@ static void amd_uncore_del(struct perf_event *event, int flags)
hwc->idx = -1;
}
+/*
+ * Convert logical cpu number to L3 PMC Config ThreadMask format
+ */
+static u64 l3_thread_slice_mask(int cpu)
+{
+ unsigned int shift, thread = 0;
+ u64 thread_mask, core = topology_core_id(cpu);
+
+ if (topology_smt_supported() && !topology_is_primary_thread(cpu))
+ thread = 1;
+
+ shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ thread_mask = BIT_ULL(shift);
+
+ return AMD64_L3_SLICE_MASK | thread_mask;
+}
+
static int amd_uncore_event_init(struct perf_event *event)
{
struct amd_uncore *uncore;
@@ -206,15 +223,8 @@ static int amd_uncore_event_init(struct perf_event *event)
* SliceMask and ThreadMask need to be set for certain L3 events in
* Family 17h. For other events, the two fields do not affect the count.
*/
- if (l3_mask && is_llc_event(event)) {
- int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
-
- if (smp_num_siblings > 1)
- thread += cpu_data(event->cpu).apicid & 1;
-
- hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
- AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
- }
+ if (l3_mask && is_llc_event(event))
+ hwc->config |= l3_thread_slice_mask(event->cpu);
uncore = event_to_amd_uncore(event);
if (!uncore)
--
2.25.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 3/3] perf/amd/uncore: Add support for Family 19h L3 PMU
2020-02-19 23:27 [PATCH 1/3] perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag Kim Phillips
2020-02-19 23:27 ` [PATCH 2/3] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support Kim Phillips
@ 2020-02-19 23:27 ` Kim Phillips
1 sibling, 0 replies; 3+ messages in thread
From: Kim Phillips @ 2020-02-19 23:27 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Ingo Molnar
Cc: Kim Phillips, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Jiri Olsa, Mark Rutland,
Michael Petlan, Namhyung Kim, Thomas Gleixner, linux-kernel, x86
Family 19h introduces a change in slice, core and thread specification
in its L3 Performance Event Select (ChL3PmcCfg) register. We implement
the new bitmask conversions in a new path in l3_thread_slice_mask()
based on a family 19h-and-above check.
We also change the uncore_init() family check to 19h-and-above, so as
to not revert to the Family 16h-or-below L2/NB code paths in the driver.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: x86@kernel.org
---
arch/x86/events/amd/uncore.c | 20 ++++++++++++++------
arch/x86/include/asm/perf_event.h | 15 +++++++++++++--
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e635c40ca9c4..78b4fb917ad6 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -191,10 +191,18 @@ static u64 l3_thread_slice_mask(int cpu)
if (topology_smt_supported() && !topology_is_primary_thread(cpu))
thread = 1;
- shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ if (boot_cpu_data.x86 <= 0x18) {
+ shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ thread_mask = BIT_ULL(shift);
+
+ return AMD64_L3_SLICE_MASK | thread_mask;
+ }
+
+ core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK;
+ shift = AMD64_L3_THREAD_SHIFT + thread;
thread_mask = BIT_ULL(shift);
- return AMD64_L3_SLICE_MASK | thread_mask;
+ return AMD64_L3_EN_ALL_SLICES | core | thread_mask;
}
static int amd_uncore_event_init(struct perf_event *event)
@@ -220,8 +228,8 @@ static int amd_uncore_event_init(struct perf_event *event)
return -EINVAL;
/*
- * SliceMask and ThreadMask need to be set for certain L3 events in
- * Family 17h. For other events, the two fields do not affect the count.
+ * SliceMask and ThreadMask need to be set for certain L3 events.
+ * For other events, the two fields do not affect the count.
*/
if (l3_mask && is_llc_event(event))
hwc->config |= l3_thread_slice_mask(event->cpu);
@@ -530,9 +538,9 @@ static int __init amd_uncore_init(void)
if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
return -ENODEV;
- if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+ if (boot_cpu_data.x86 >= 0x17) {
/*
- * For F17h or F18h, the Northbridge counters are
+ * For F17h and above, the Northbridge counters are
* repurposed as Data Fabric counters. Also, L3
* counters are supported too. The PMUs are exported
* based on family as either L2 or L3 and NB or DF.
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 29964b0e1075..e855e9cf2c37 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -50,11 +50,22 @@
#define AMD64_L3_SLICE_SHIFT 48
#define AMD64_L3_SLICE_MASK \
- ((0xFULL) << AMD64_L3_SLICE_SHIFT)
+ (0xFULL << AMD64_L3_SLICE_SHIFT)
+#define AMD64_L3_SLICEID_MASK \
+ (0x7ULL << AMD64_L3_SLICE_SHIFT)
#define AMD64_L3_THREAD_SHIFT 56
#define AMD64_L3_THREAD_MASK \
- ((0xFFULL) << AMD64_L3_THREAD_SHIFT)
+ (0xFFULL << AMD64_L3_THREAD_SHIFT)
+#define AMD64_L3_F19H_THREAD_MASK \
+ (0x3ULL << AMD64_L3_THREAD_SHIFT)
+
+#define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
+#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
+
+#define AMD64_L3_COREID_SHIFT 42
+#define AMD64_L3_COREID_MASK \
+ (0x7ULL << AMD64_L3_COREID_SHIFT)
#define X86_RAW_EVENT_MASK \
(ARCH_PERFMON_EVENTSEL_EVENT | \
--
2.25.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-02-19 23:28 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-02-19 23:27 [PATCH 1/3] perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag Kim Phillips
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2020-02-19 23:27 ` [PATCH 3/3] perf/amd/uncore: Add support for Family 19h L3 PMU Kim Phillips
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