From: Heyi Guo <guoheyi@huawei.com>
To: <linux-kernel@vger.kernel.org>
Cc: <wanghaibin.wang@huawei.com>, Heyi Guo <guoheyi@huawei.com>,
Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Subject: [PATCH] irq-gic-v3-its: fix access width for gicr_syncr
Date: Tue, 25 Feb 2020 17:00:23 +0800 [thread overview]
Message-ID: <20200225090023.28020-1-guoheyi@huawei.com> (raw)
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
---
Cc: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 65a11257d220..5c6790e3bfbf 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase)
{
- while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+ while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}
--
2.19.1
next reply other threads:[~2020-02-25 9:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 9:00 Heyi Guo [this message]
2020-02-25 16:17 ` [PATCH] irq-gic-v3-its: fix access width for gicr_syncr Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] irqchip/gic-v3-its: Fix " tip-bot2 for Heyi Guo
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