* [PATCH] irq-gic-v3-its: fix access width for gicr_syncr
@ 2020-02-25 9:00 Heyi Guo
2020-02-25 16:17 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] irqchip/gic-v3-its: Fix " tip-bot2 for Heyi Guo
0 siblings, 2 replies; 3+ messages in thread
From: Heyi Guo @ 2020-02-25 9:00 UTC (permalink / raw)
To: linux-kernel
Cc: wanghaibin.wang, Heyi Guo, Marc Zyngier, Thomas Gleixner, Jason Cooper
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
---
Cc: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 65a11257d220..5c6790e3bfbf 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase)
{
- while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+ while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}
--
2.19.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] irq-gic-v3-its: fix access width for gicr_syncr
2020-02-25 9:00 [PATCH] irq-gic-v3-its: fix access width for gicr_syncr Heyi Guo
@ 2020-02-25 16:17 ` Marc Zyngier
2020-03-29 20:26 ` [tip: irq/core] irqchip/gic-v3-its: Fix " tip-bot2 for Heyi Guo
1 sibling, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2020-02-25 16:17 UTC (permalink / raw)
To: Heyi Guo; +Cc: linux-kernel, wanghaibin.wang, Thomas Gleixner, Jason Cooper
On 2020-02-25 09:00, Heyi Guo wrote:
> GICR_SYNCR is a 32bit register, so it is better to access it with
> 32bit access width, though we have not seen any real problem.
>
> Signed-off-by: Heyi Guo <guoheyi@huawei.com>
>
> ---
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index 65a11257d220..5c6790e3bfbf 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d,
> u8 clr, u8 set)
>
> static void wait_for_syncr(void __iomem *rdbase)
> {
> - while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
> + while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
> cpu_relax();
> }
Yup, nice catch. Looks like no implementation really cares about it,
but still worth fixing.
I'll take it for 5.7.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 3+ messages in thread
* [tip: irq/core] irqchip/gic-v3-its: Fix access width for gicr_syncr
2020-02-25 9:00 [PATCH] irq-gic-v3-its: fix access width for gicr_syncr Heyi Guo
2020-02-25 16:17 ` Marc Zyngier
@ 2020-03-29 20:26 ` tip-bot2 for Heyi Guo
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot2 for Heyi Guo @ 2020-03-29 20:26 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Heyi Guo, Marc Zyngier, x86, LKML
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 04d80dbe858d801efbecf3e5172b31b0a3757308
Gitweb: https://git.kernel.org/tip/04d80dbe858d801efbecf3e5172b31b0a3757308
Author: Heyi Guo <guoheyi@huawei.com>
AuthorDate: Tue, 25 Feb 2020 17:00:23 +08:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sun, 08 Mar 2020 14:25:46
irqchip/gic-v3-its: Fix access width for gicr_syncr
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 83b1186..6bb2bea 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase)
{
- while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+ while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}
^ permalink raw reply related [flat|nested] 3+ messages in thread
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