From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Sergey.Semin@baikalelectronics.ru
Cc: Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>,
Vadim Vlasov <V.Vlasov@baikalelectronics.ru>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>,
Viresh Kumar <vireshk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/5] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account
Date: Fri, 6 Mar 2020 15:29:12 +0200 [thread overview]
Message-ID: <20200306132912.GA1748204@smile.fi.intel.com> (raw)
In-Reply-To: <20200306131048.ADBE18030797@mail.baikalelectronics.ru>
On Fri, Mar 06, 2020 at 04:10:29PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <fancer.lancer@gmail.com>
>
> Baikal-T1 SoC has an DW DMAC on-board to provide a Mem-to-Mem, low-speed
> peripherals Dev-to-Mem and Mem-to-Dev functionality. Mostly it's compatible
> with currently implemented in the kernel DW DMAC driver, but there are some
> peculiarities which must be taken into account in order to have the device
> fully supported.
>
> First of all traditionally we replaced the legacy plain text-based dt-binding
> file with yaml-based one. Secondly Baikal-T1 DW DMA Controller provides eight
> channels, which alas have different max burst length configuration.
> In particular first two channels may burst up to 128 bits (16 bytes) at a time
> while the rest of them just up to 32 bits. We must make sure that the DMA
> subsystem doesn't set values exceeding these limitations otherwise the
> controller will hang up. In third currently we discovered the problem in using
> the DW APB SPI driver together with DW DMAC. The problem happens if there is no
> natively implemented multi-block LLP transfers support and the SPI-transfer
> length exceeds the max lock size. In this case due to asynchronous handling of
> Tx- and Rx- SPI transfers interrupt we might end up with Dw APB SSI Rx FIFO
> overflow. So if DW APB SSI (or any other DMAC service consumer) intends to use
> the DMAC to asynchronously execute the transfers we'd have to at least warn
> the user of the possible errors.
>
> Finally there is a bug in the algorithm of the nollp flag detection.
> In particular even if DW DMAC parameters state the multi-block transfers
> support there is still HC_LLP (hardcode LLP) flag, which if set makes expected
> by the driver true multi-block LLP functionality unusable. This happens cause'
> if HC_LLP flag is set the LLP registers will be hardcoded to zero so the
> contiguous multi-block transfers will be only supported. We must take the
> flag into account when detecting the LLP support otherwise the driver just
> won't work correctly.
>
> This patchset is rebased and tested on the mainline Linux kernel 5.6-rc4:
> commit 98d54f81e36b ("Linux 5.6-rc4").
Thank you for your series!
I'll definitely review it, but it will take time. So, I think due to late
submission this is material at least for v5.8.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
> Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Viresh Kumar <vireshk@kernel.org>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: dmaengine@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> Serge Semin (5):
> dt-bindings: dma: dw: Replace DW DMAC legacy bindings with YAML-based
> one
> dt-bindings: dma: dw: Add max burst transaction length property
> bindings
> dmaengine: dw: Add LLP and block size config accessors
> dmaengine: dw: Introduce max burst length hw config
> dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config
>
> .../bindings/dma/snps,dma-spear1340.yaml | 180 ++++++++++++++++++
> .../devicetree/bindings/dma/snps-dma.txt | 69 -------
> drivers/dma/dw/core.c | 24 ++-
> drivers/dma/dw/dw.c | 1 +
> drivers/dma/dw/of.c | 9 +
> drivers/dma/dw/regs.h | 3 +
> include/linux/platform_data/dma-dw.h | 22 +++
> 7 files changed, 238 insertions(+), 70 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
> delete mode 100644 Documentation/devicetree/bindings/dma/snps-dma.txt
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-03-06 13:29 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 13:10 [PATCH 0/5] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account Sergey.Semin
2020-03-06 13:29 ` Andy Shevchenko [this message]
2020-03-06 13:30 ` Andy Shevchenko
2020-03-06 13:43 ` Vinod Koul
[not found] ` <20200306135050.40094803087C@mail.baikalelectronics.ru>
2020-03-09 21:45 ` Sergey Semin
[not found] ` <20200306133756.0F74C8030793@mail.baikalelectronics.ru>
2020-03-06 13:47 ` Sergey Semin
2020-03-06 14:11 ` Andy Shevchenko
[not found] ` <20200306141135.9C4F380307C2@mail.baikalelectronics.ru>
2020-03-09 22:08 ` Sergey Semin
2020-05-08 10:52 ` [PATCH v2 0/6] " Serge Semin
2020-05-08 10:52 ` [PATCH v2 1/6] dt-bindings: dma: dw: Convert DW DMAC to DT binding Serge Semin
2020-05-18 17:50 ` Rob Herring
2020-05-08 10:53 ` [PATCH v2 2/6] dt-bindings: dma: dw: Add max burst transaction length property Serge Semin
2020-05-08 11:12 ` Andy Shevchenko
2020-05-11 20:05 ` Serge Semin
2020-05-11 21:01 ` Andy Shevchenko
2020-05-11 21:35 ` Serge Semin
2020-05-12 9:08 ` Andy Shevchenko
2020-05-12 11:49 ` Serge Semin
2020-05-12 12:38 ` Andy Shevchenko
2020-05-15 6:09 ` Vinod Koul
2020-05-15 10:51 ` Andy Shevchenko
2020-05-15 10:56 ` Vinod Koul
2020-05-15 11:11 ` Serge Semin
2020-05-17 17:47 ` Serge Semin
2020-05-18 17:30 ` Rob Herring
2020-05-18 19:30 ` Serge Semin
2020-05-19 17:13 ` Vinod Koul
2020-05-21 1:33 ` Serge Semin
2020-05-08 10:53 ` [PATCH v2 3/6] dmaengine: dw: Set DMA device max segment size parameter Serge Semin
2020-05-08 11:21 ` Andy Shevchenko
2020-05-08 18:49 ` Vineet Gupta
2020-05-11 21:16 ` Serge Semin
2020-05-12 12:35 ` Andy Shevchenko
2020-05-12 17:01 ` Serge Semin
2020-05-15 6:16 ` Vinod Koul
2020-05-15 10:53 ` Andy Shevchenko
2020-05-17 18:22 ` Serge Semin
2020-05-08 10:53 ` [PATCH v2 4/6] dmaengine: dw: Print warning if multi-block is unsupported Serge Semin
2020-05-08 11:26 ` Andy Shevchenko
2020-05-08 11:53 ` Mark Brown
2020-05-08 19:06 ` Andy Shevchenko
2020-05-11 3:13 ` Serge Semin
2020-05-11 14:03 ` Andy Shevchenko
2020-05-11 2:10 ` Serge Semin
2020-05-11 11:58 ` Mark Brown
2020-05-11 13:45 ` Serge Semin
2020-05-11 13:58 ` Andy Shevchenko
2020-05-11 17:48 ` Mark Brown
2020-05-11 18:25 ` Serge Semin
2020-05-11 19:32 ` Serge Semin
2020-05-11 21:07 ` Andy Shevchenko
2020-05-11 21:08 ` Andy Shevchenko
2020-05-12 12:42 ` Serge Semin
2020-05-15 6:30 ` Vinod Koul
2020-05-17 19:23 ` Serge Semin
2020-05-19 17:02 ` Vinod Koul
2020-05-21 1:40 ` Serge Semin
2020-05-11 17:44 ` Mark Brown
2020-05-11 18:32 ` Serge Semin
2020-05-11 21:32 ` Mark Brown
2020-05-08 10:53 ` [PATCH v2 5/6] dmaengine: dw: Introduce max burst length hw config Serge Semin
2020-05-08 11:41 ` Andy Shevchenko
2020-05-12 14:08 ` Serge Semin
2020-05-12 19:12 ` Andy Shevchenko
2020-05-12 19:47 ` Serge Semin
2020-05-15 11:02 ` Andy Shevchenko
2020-05-15 6:39 ` Vinod Koul
2020-05-17 19:38 ` Serge Semin
2020-05-19 17:07 ` Vinod Koul
2020-05-21 1:47 ` Serge Semin
2020-05-08 10:53 ` [PATCH v2 6/6] dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config Serge Semin
2020-05-08 11:43 ` Andy Shevchenko
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