* [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
@ 2020-02-07 22:33 Kamal Dasu
2020-02-07 22:35 ` Florian Fainelli
2020-03-11 20:54 ` Florian Fainelli
0 siblings, 2 replies; 6+ messages in thread
From: Kamal Dasu @ 2020-02-07 22:33 UTC (permalink / raw)
To: linux-mips, bcm-kernel-feedback-list
Cc: Ralf Baechle, Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
line can contain two instruction cache lines (64B), or four data cache
lines (32B). Hardware prefetch Cache detects stream access, and prefetches
ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
secondary cache module (ZSCM) on DMA from device so that data returned is
coherent during DMA read operations.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
arch/mips/mm/c-r4k.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5f3d0103b95d..acd9ef383e97 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
__sync();
}
+static void prefetch_cache_inv(unsigned long addr, unsigned long size)
+{
+ unsigned int linesz = cpu_scache_line_size();
+ unsigned long addr0 = addr, addr1;
+
+ addr0 &= ~(linesz - 1);
+ addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+ protected_writeback_scache_line(addr0);
+ if (likely(addr1 != addr0))
+ protected_writeback_scache_line(addr1);
+ else
+ return;
+
+ addr0 += linesz;
+ if (likely(addr1 != addr0))
+ protected_writeback_scache_line(addr0);
+ else
+ return;
+
+ addr1 -= linesz;
+ if (likely(addr1 > addr0))
+ protected_writeback_scache_line(addr0);
+}
+
static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
{
/* Catch bad driver code */
@@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
return;
preempt_disable();
+
+ if (current_cpu_type() == CPU_BMIPS5000)
+ prefetch_cache_inv(addr, size);
+
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) {
if (current_cpu_type() != CPU_LOONGSON64)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
2020-02-07 22:33 [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
@ 2020-02-07 22:35 ` Florian Fainelli
2020-03-11 20:54 ` Florian Fainelli
1 sibling, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2020-02-07 22:35 UTC (permalink / raw)
To: Kamal Dasu, linux-mips, bcm-kernel-feedback-list
Cc: Ralf Baechle, Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
On 2/7/20 2:33 PM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.
>
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Thanks Kamal!
--
Florian
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
2020-02-07 22:33 [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
2020-02-07 22:35 ` Florian Fainelli
@ 2020-03-11 20:54 ` Florian Fainelli
2020-03-11 21:44 ` Thomas Bogendoerfer
1 sibling, 1 reply; 6+ messages in thread
From: Florian Fainelli @ 2020-03-11 20:54 UTC (permalink / raw)
To: Kamal Dasu, linux-mips, bcm-kernel-feedback-list, Thomas Bogendoerfer
Cc: Ralf Baechle, Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
On 2/7/20 2:33 PM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.
>
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Thomas can review and apply this patch? Thank you!
> ---
> arch/mips/mm/c-r4k.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 5f3d0103b95d..acd9ef383e97 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
> __sync();
> }
>
> +static void prefetch_cache_inv(unsigned long addr, unsigned long size)
> +{
> + unsigned int linesz = cpu_scache_line_size();
> + unsigned long addr0 = addr, addr1;
> +
> + addr0 &= ~(linesz - 1);
> + addr1 = (addr0 + size - 1) & ~(linesz - 1);
> +
> + protected_writeback_scache_line(addr0);
> + if (likely(addr1 != addr0))
> + protected_writeback_scache_line(addr1);
> + else
> + return;
> +
> + addr0 += linesz;
> + if (likely(addr1 != addr0))
> + protected_writeback_scache_line(addr0);
> + else
> + return;
> +
> + addr1 -= linesz;
> + if (likely(addr1 > addr0))
> + protected_writeback_scache_line(addr0);
> +}
> +
> static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
> {
> /* Catch bad driver code */
> @@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
> return;
>
> preempt_disable();
> +
> + if (current_cpu_type() == CPU_BMIPS5000)
> + prefetch_cache_inv(addr, size);
> +
> if (cpu_has_inclusive_pcaches) {
> if (size >= scache_size) {
> if (current_cpu_type() != CPU_LOONGSON64)
>
--
Florian
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
2020-03-11 20:54 ` Florian Fainelli
@ 2020-03-11 21:44 ` Thomas Bogendoerfer
2020-03-13 3:09 ` Kamal Dasu
0 siblings, 1 reply; 6+ messages in thread
From: Thomas Bogendoerfer @ 2020-03-11 21:44 UTC (permalink / raw)
To: Florian Fainelli
Cc: Kamal Dasu, linux-mips, bcm-kernel-feedback-list, Ralf Baechle,
Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
> On 2/7/20 2:33 PM, Kamal Dasu wrote:
> > Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> > line can contain two instruction cache lines (64B), or four data cache
> > lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> > ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> > secondary cache module (ZSCM) on DMA from device so that data returned is
> > coherent during DMA read operations.
> >
> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>
> Thomas can review and apply this patch? Thank you!
looks good to me. I only wonder whether r4k_dma_cache_wbinv() also
needs this ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
2020-03-11 21:44 ` Thomas Bogendoerfer
@ 2020-03-13 3:09 ` Kamal Dasu
2020-03-16 15:31 ` Thomas Bogendoerfer
0 siblings, 1 reply; 6+ messages in thread
From: Kamal Dasu @ 2020-03-13 3:09 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: Florian Fainelli, linux-mips, bcm-kernel-feedback-list,
Ralf Baechle, Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
This is needed on dma reads from device.
Kamal
> On Mar 11, 2020, at 5:44 PM, Thomas Bogendoerfer <tsbogend@alpha.franken.de> wrote:
>
> On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
>>> On 2/7/20 2:33 PM, Kamal Dasu wrote:
>>> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
>>> line can contain two instruction cache lines (64B), or four data cache
>>> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
>>> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
>>> secondary cache module (ZSCM) on DMA from device so that data returned is
>>> coherent during DMA read operations.
>>>
>>> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>>
>> Thomas can review and apply this patch? Thank you!
>
> looks good to me. I only wonder whether r4k_dma_cache_wbinv() also
> needs this ?
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
2020-03-13 3:09 ` Kamal Dasu
@ 2020-03-16 15:31 ` Thomas Bogendoerfer
0 siblings, 0 replies; 6+ messages in thread
From: Thomas Bogendoerfer @ 2020-03-16 15:31 UTC (permalink / raw)
To: Kamal Dasu
Cc: Florian Fainelli, linux-mips, bcm-kernel-feedback-list,
Ralf Baechle, Paul Burton, James Hogan, Jiaxun Yang, Huacai Chen,
Mike Rapoport, linux-kernel
On Thu, Mar 12, 2020 at 11:09:35PM -0400, Kamal Dasu wrote:
> This is needed on dma reads from device.
ok.
> > On Mar 11, 2020, at 5:44 PM, Thomas Bogendoerfer <tsbogend@alpha.franken.de> wrote:
> >
> > On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
> >>> On 2/7/20 2:33 PM, Kamal Dasu wrote:
> >>> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> >>> line can contain two instruction cache lines (64B), or four data cache
> >>> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> >>> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> >>> secondary cache module (ZSCM) on DMA from device so that data returned is
> >>> coherent during DMA read operations.
> >>>
> >>> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 6+ messages in thread
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2020-02-07 22:33 [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
2020-02-07 22:35 ` Florian Fainelli
2020-03-11 20:54 ` Florian Fainelli
2020-03-11 21:44 ` Thomas Bogendoerfer
2020-03-13 3:09 ` Kamal Dasu
2020-03-16 15:31 ` Thomas Bogendoerfer
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