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From: Dinh Nguyen <dinguyen@kernel.org>
To: linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, sboyd@kernel.org,
	mturquette@baylibre.com, robh+dt@kernel.org,
	mark.rutland@arm.com, Dinh Nguyen <dinh.nguyen@intel.com>
Subject: [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods
Date: Tue, 17 Mar 2020 11:10:19 -0500	[thread overview]
Message-ID: <20200317161022.11181-3-dinguyen@kernel.org> (raw)
In-Reply-To: <20200317161022.11181-1-dinguyen@kernel.org>

From: Dinh Nguyen <dinh.nguyen@intel.com>

The enable/disable clock ops are already defined in the standard clock
ops, so we don't need to assign them.

Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
---
 drivers/clk/socfpga/clk-pll-a10.c | 2 --
 drivers/clk/socfpga/clk-pll-s10.c | 2 --
 drivers/clk/socfpga/clk-pll.c     | 2 --
 3 files changed, 6 deletions(-)

diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 3816fc04b274..6d9395106c0c 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index bcd3f14e9145..9faa80ff3b53 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index dc65cc0fd3bd..a001641b2f42 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
-- 
2.25.1


  parent reply	other threads:[~2020-03-17 16:10 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-17 16:10 [PATCHv3 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-03-17 16:10 ` [PATCHv2 1/5] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-03-17 16:10 ` Dinh Nguyen [this message]
2020-03-17 16:10 ` [PATCH 3/5] clk: socfpga: add const to _ops data structures Dinh Nguyen
2020-03-17 16:10 ` [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-18 22:40   ` Rob Herring
2020-03-19 16:16     ` Dinh Nguyen
2020-03-19 16:56       ` Rob Herring
2020-03-19 19:18         ` Dinh Nguyen
2020-03-17 16:10 ` [PATCHv3 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
2020-03-20 17:02 [PATCHv4 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-03-20 17:02 ` [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods Dinh Nguyen

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