From: Dinh Nguyen <dinguyen@kernel.org>
To: linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, sboyd@kernel.org,
mturquette@baylibre.com, robh+dt@kernel.org,
mark.rutland@arm.com, Dinh Nguyen <dinh.nguyen@intel.com>
Subject: [PATCH 3/5] clk: socfpga: add const to _ops data structures
Date: Tue, 17 Mar 2020 11:10:20 -0500 [thread overview]
Message-ID: <20200317161022.11181-4-dinguyen@kernel.org> (raw)
In-Reply-To: <20200317161022.11181-1-dinguyen@kernel.org>
From: Dinh Nguyen <dinh.nguyen@intel.com>
All the static clk_ops data structure need a const.
Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
---
drivers/clk/socfpga/clk-pll-a10.c | 2 +-
drivers/clk/socfpga/clk-pll-s10.c | 4 ++--
drivers/clk/socfpga/clk-pll.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 6d9395106c0c..db54f7d806a0 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
CLK_MGR_PLL_CLK_SRC_MASK;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
};
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 9faa80ff3b53..5c3e1ee44f6b 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
return 0;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = clk_pll_prepare,
};
-static struct clk_ops clk_boot_ops = {
+static const struct clk_ops clk_boot_ops = {
.recalc_rate = clk_boot_clk_recalc_rate,
.get_parent = clk_boot_get_parent,
.prepare = clk_pll_prepare,
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index a001641b2f42..e5fb786843f3 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
CLK_MGR_PLL_CLK_SRC_MASK;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
};
--
2.25.1
next prev parent reply other threads:[~2020-03-17 16:10 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-17 16:10 [PATCHv3 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-03-17 16:10 ` [PATCHv2 1/5] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-03-17 16:10 ` [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods Dinh Nguyen
2020-03-17 16:10 ` Dinh Nguyen [this message]
2020-03-17 16:10 ` [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-18 22:40 ` Rob Herring
2020-03-19 16:16 ` Dinh Nguyen
2020-03-19 16:56 ` Rob Herring
2020-03-19 19:18 ` Dinh Nguyen
2020-03-17 16:10 ` [PATCHv3 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
2020-03-20 17:02 [PATCHv4 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-03-20 17:02 ` [PATCH 3/5] clk: socfpga: add const to _ops data structures Dinh Nguyen
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