From: "Mylène Josserand" <mylene.josserand@collabora.com>
To: heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
mturquette@baylibre.com, sboyd@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-clk@vger.kernel.org, mylene.josserand@collabora.com,
kernel@collabora.com, kever.yang@rock-chips.com,
geert@linux-m68k.org
Subject: [PATCH v2 2/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
Date: Wed, 1 Apr 2020 17:35:13 +0200 [thread overview]
Message-ID: <20200401153513.423683-3-mylene.josserand@collabora.com> (raw)
In-Reply-To: <20200401153513.423683-1-mylene.josserand@collabora.com>
The revision rk3288w has a different clock tree about
"hclk_vio" clock, according to the BSP kernel code.
This patch handles this difference by detecting which SOC it is
and creating the div accordingly. Because we are using
soc_device_match function, we need to delay the registration
of this clock later than others to have time to get SoC revision.
Otherwise, because of CLK_OF_DECLARE uses, clock tree will be
created too soon to have time to detect SoC's revision.
Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
---
drivers/clk/rockchip/clk-rk3288.c | 36 +++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index cc2a177bbdbf..1950d1efe1b8 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -9,6 +9,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
+#include <linux/sys_soc.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
@@ -425,8 +426,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 0, GFLAGS),
- DIV(0, "hclk_vio", "aclk_vio0", 0,
- RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 2, GFLAGS),
@@ -819,6 +818,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
};
+static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
+ DIV(0, "hclk_vio", "aclk_vio1", 0,
+ RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
+static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
+ DIV(0, "hclk_vio", "aclk_vio0", 0,
+ RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
static const char *const rk3288_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
@@ -914,10 +923,15 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
.resume = rk3288_clk_resume,
};
+static const struct soc_device_attribute rk3288w[] = {
+ { .soc_id = "RK32xx", .revision = "RK3288w" },
+ { /* sentinel */ }
+};
+
+static struct rockchip_clk_provider *ctx;
+
static void __init rk3288_clk_init(struct device_node *np)
{
- struct rockchip_clk_provider *ctx;
-
rk3288_cru_base = of_iomap(np, 0);
if (!rk3288_cru_base) {
pr_err("%s: could not map cru region\n", __func__);
@@ -955,3 +969,17 @@ static void __init rk3288_clk_init(struct device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
+
+static int __init rk3288_hclkvio_register(void)
+{
+ /* Check for the rk3288w revision as clock tree is different */
+ if (soc_device_match(rk3288w))
+ rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
+ ARRAY_SIZE(rk3288w_hclkvio_branch));
+ else
+ rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
+ ARRAY_SIZE(rk3288_hclkvio_branch));
+
+ return 0;
+}
+subsys_initcall(rk3288_hclkvio_register);
--
2.25.1
next prev parent reply other threads:[~2020-04-01 15:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-01 15:35 [PATCH v2 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand
2020-04-01 15:35 ` [PATCH v2 1/2] soc: rockchip: Register a soc_device to retrieve revision Mylène Josserand
2020-04-01 16:34 ` Heiko Stübner
2020-04-02 6:31 ` Mylene Josserand
2020-04-02 11:45 ` Robin Murphy
2020-04-02 14:14 ` Heiko Stübner
2020-04-01 15:35 ` Mylène Josserand [this message]
2020-04-01 16:56 ` [PATCH v2 2/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Geert Uytterhoeven
2020-04-02 6:35 ` Mylene Josserand
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