* [PATCH 1/4] x86/mm: Add a x86_has_pat_wp helper
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
@ 2020-04-08 15:27 ` Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] x86/mm: Add a x86_has_pat_wp() helper tip-bot2 for Christoph Hellwig
2020-04-08 15:27 ` [PATCH 2/4] x86/mm: Move pgprot2cachemode out of line Christoph Hellwig
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Christoph Hellwig @ 2020-04-08 15:27 UTC (permalink / raw)
To: x86, Dave Hansen, Andy Lutomirski, Peter Zijlstra, linux-kernel
Abstract the ioremap code away from the caching mode internals.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/x86/include/asm/memtype.h | 2 ++
arch/x86/mm/init.c | 6 ++++++
arch/x86/mm/ioremap.c | 8 ++------
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h
index 9c2447b3555d..1e4e99b40711 100644
--- a/arch/x86/include/asm/memtype.h
+++ b/arch/x86/include/asm/memtype.h
@@ -24,4 +24,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end);
extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn);
+bool x86_has_pat_wp(void);
+
#endif /* _ASM_X86_MEMTYPE_H */
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index e7bb483557c9..83e5780768ad 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -71,6 +71,12 @@ uint8_t __pte2cachemode_tbl[8] = {
};
EXPORT_SYMBOL(__pte2cachemode_tbl);
+/* Check that the write-protect PAT entry is set for write-protect */
+bool x86_has_pat_wp(void)
+{
+ return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
+}
+
static unsigned long __initdata pgt_buf_start;
static unsigned long __initdata pgt_buf_end;
static unsigned long __initdata pgt_buf_top;
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 18c637c0dc6f..41536f523a5f 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -778,10 +778,8 @@ void __init *early_memremap_encrypted(resource_size_t phys_addr,
void __init *early_memremap_encrypted_wp(resource_size_t phys_addr,
unsigned long size)
{
- /* Be sure the write-protect PAT entry is set for write-protect */
- if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP)
+ if (!x86_has_pat_wp())
return NULL;
-
return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_ENC_WP);
}
@@ -799,10 +797,8 @@ void __init *early_memremap_decrypted(resource_size_t phys_addr,
void __init *early_memremap_decrypted_wp(resource_size_t phys_addr,
unsigned long size)
{
- /* Be sure the write-protect PAT entry is set for write-protect */
- if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP)
+ if (!x86_has_pat_wp())
return NULL;
-
return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_NOENC_WP);
}
#endif /* CONFIG_AMD_MEM_ENCRYPT */
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Add a x86_has_pat_wp() helper
2020-04-08 15:27 ` [PATCH 1/4] x86/mm: Add a x86_has_pat_wp helper Christoph Hellwig
@ 2020-04-20 13:30 ` tip-bot2 for Christoph Hellwig
0 siblings, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-20 13:30 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: 1f6f655e01adebf5bd5e6c3da2e843c104ded051
Gitweb: https://git.kernel.org/tip/1f6f655e01adebf5bd5e6c3da2e843c104ded051
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:42 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 20 Apr 2020 12:39:11 +02:00
x86/mm: Add a x86_has_pat_wp() helper
Abstract the ioremap code away from the caching mode internals.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-2-hch@lst.de
---
arch/x86/include/asm/memtype.h | 2 ++
arch/x86/mm/init.c | 6 ++++++
arch/x86/mm/ioremap.c | 8 ++------
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h
index 9c2447b..1e4e99b 100644
--- a/arch/x86/include/asm/memtype.h
+++ b/arch/x86/include/asm/memtype.h
@@ -24,4 +24,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end);
extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn);
+bool x86_has_pat_wp(void);
+
#endif /* _ASM_X86_MEMTYPE_H */
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 1bba16c..6005f83 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -71,6 +71,12 @@ uint8_t __pte2cachemode_tbl[8] = {
};
EXPORT_SYMBOL(__pte2cachemode_tbl);
+/* Check that the write-protect PAT entry is set for write-protect */
+bool x86_has_pat_wp(void)
+{
+ return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
+}
+
static unsigned long __initdata pgt_buf_start;
static unsigned long __initdata pgt_buf_end;
static unsigned long __initdata pgt_buf_top;
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 18c637c..41536f5 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -778,10 +778,8 @@ void __init *early_memremap_encrypted(resource_size_t phys_addr,
void __init *early_memremap_encrypted_wp(resource_size_t phys_addr,
unsigned long size)
{
- /* Be sure the write-protect PAT entry is set for write-protect */
- if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP)
+ if (!x86_has_pat_wp())
return NULL;
-
return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_ENC_WP);
}
@@ -799,10 +797,8 @@ void __init *early_memremap_decrypted(resource_size_t phys_addr,
void __init *early_memremap_decrypted_wp(resource_size_t phys_addr,
unsigned long size)
{
- /* Be sure the write-protect PAT entry is set for write-protect */
- if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP)
+ if (!x86_has_pat_wp())
return NULL;
-
return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_NOENC_WP);
}
#endif /* CONFIG_AMD_MEM_ENCRYPT */
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/4] x86/mm: Move pgprot2cachemode out of line
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
2020-04-08 15:27 ` [PATCH 1/4] x86/mm: Add a x86_has_pat_wp helper Christoph Hellwig
@ 2020-04-08 15:27 ` Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] " tip-bot2 for Christoph Hellwig
2020-04-08 15:27 ` [PATCH 3/4] x86/mm: Cleanup pgprot_4k_2_large and pgprot_large_2_4k Christoph Hellwig
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Christoph Hellwig @ 2020-04-08 15:27 UTC (permalink / raw)
To: x86, Dave Hansen, Andy Lutomirski, Peter Zijlstra, linux-kernel
This helper is only used by x86 low-level MM code. Also remove the
entirely pointless __pte2cachemode_tbl export as that symbol can be
marked static now.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/x86/include/asm/memtype.h | 1 +
arch/x86/include/asm/pgtable_types.h | 10 ----------
arch/x86/mm/init.c | 13 +++++++++++--
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h
index 1e4e99b40711..9ca760e430b9 100644
--- a/arch/x86/include/asm/memtype.h
+++ b/arch/x86/include/asm/memtype.h
@@ -25,5 +25,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end);
extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn);
bool x86_has_pat_wp(void);
+enum page_cache_mode pgprot2cachemode(pgprot_t pgprot);
#endif /* _ASM_X86_MEMTYPE_H */
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index b6606fe6cfdf..75fe903124f8 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -468,7 +468,6 @@ static inline pteval_t pte_flags(pte_t pte)
}
extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
-extern uint8_t __pte2cachemode_tbl[8];
#define __pte2cm_idx(cb) \
((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
@@ -489,15 +488,6 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
return __pgprot(cachemode2protval(pcm));
}
-static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
-{
- unsigned long masked;
-
- masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
- if (likely(masked == 0))
- return 0;
- return __pte2cachemode_tbl[__pte2cm_idx(masked)];
-}
static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
{
pgprotval_t val = pgprot_val(pgprot);
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 83e5780768ad..8482ee51b225 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -59,7 +59,7 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
};
EXPORT_SYMBOL(__cachemode2pte_tbl);
-uint8_t __pte2cachemode_tbl[8] = {
+static uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
[__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
@@ -69,7 +69,6 @@ uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
};
-EXPORT_SYMBOL(__pte2cachemode_tbl);
/* Check that the write-protect PAT entry is set for write-protect */
bool x86_has_pat_wp(void)
@@ -77,6 +76,16 @@ bool x86_has_pat_wp(void)
return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
}
+enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
+{
+ unsigned long masked;
+
+ masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
+ if (likely(masked == 0))
+ return 0;
+ return __pte2cachemode_tbl[__pte2cm_idx(masked)];
+}
+
static unsigned long __initdata pgt_buf_start;
static unsigned long __initdata pgt_buf_end;
static unsigned long __initdata pgt_buf_top;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Move pgprot2cachemode out of line
2020-04-08 15:27 ` [PATCH 2/4] x86/mm: Move pgprot2cachemode out of line Christoph Hellwig
@ 2020-04-20 13:30 ` tip-bot2 for Christoph Hellwig
0 siblings, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-20 13:30 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: 7fa3e10f0f3646108a1018004d0f571c3222dc9f
Gitweb: https://git.kernel.org/tip/7fa3e10f0f3646108a1018004d0f571c3222dc9f
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:43 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 20 Apr 2020 12:39:17 +02:00
x86/mm: Move pgprot2cachemode out of line
This helper is only used by x86 low-level MM code. Also remove the
entirely pointless __pte2cachemode_tbl export as that symbol can be
marked static now.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-3-hch@lst.de
---
arch/x86/include/asm/memtype.h | 1 +
arch/x86/include/asm/pgtable_types.h | 10 ----------
arch/x86/mm/init.c | 13 +++++++++++--
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h
index 1e4e99b..9ca760e 100644
--- a/arch/x86/include/asm/memtype.h
+++ b/arch/x86/include/asm/memtype.h
@@ -25,5 +25,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end);
extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn);
bool x86_has_pat_wp(void);
+enum page_cache_mode pgprot2cachemode(pgprot_t pgprot);
#endif /* _ASM_X86_MEMTYPE_H */
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index b6606fe..75fe903 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -468,7 +468,6 @@ static inline pteval_t pte_flags(pte_t pte)
}
extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
-extern uint8_t __pte2cachemode_tbl[8];
#define __pte2cm_idx(cb) \
((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
@@ -489,15 +488,6 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
return __pgprot(cachemode2protval(pcm));
}
-static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
-{
- unsigned long masked;
-
- masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
- if (likely(masked == 0))
- return 0;
- return __pte2cachemode_tbl[__pte2cm_idx(masked)];
-}
static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
{
pgprotval_t val = pgprot_val(pgprot);
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 6005f83..4a55d68 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -59,7 +59,7 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
};
EXPORT_SYMBOL(__cachemode2pte_tbl);
-uint8_t __pte2cachemode_tbl[8] = {
+static uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
[__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
@@ -69,7 +69,6 @@ uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
};
-EXPORT_SYMBOL(__pte2cachemode_tbl);
/* Check that the write-protect PAT entry is set for write-protect */
bool x86_has_pat_wp(void)
@@ -77,6 +76,16 @@ bool x86_has_pat_wp(void)
return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
}
+enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
+{
+ unsigned long masked;
+
+ masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
+ if (likely(masked == 0))
+ return 0;
+ return __pte2cachemode_tbl[__pte2cm_idx(masked)];
+}
+
static unsigned long __initdata pgt_buf_start;
static unsigned long __initdata pgt_buf_end;
static unsigned long __initdata pgt_buf_top;
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/4] x86/mm: Cleanup pgprot_4k_2_large and pgprot_large_2_4k
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
2020-04-08 15:27 ` [PATCH 1/4] x86/mm: Add a x86_has_pat_wp helper Christoph Hellwig
2020-04-08 15:27 ` [PATCH 2/4] x86/mm: Move pgprot2cachemode out of line Christoph Hellwig
@ 2020-04-08 15:27 ` Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k() tip-bot2 for Christoph Hellwig
2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
2020-04-08 15:27 ` [PATCH 4/4] x86/mm: Unexport __cachemode2pte_tbl Christoph Hellwig
` (2 subsequent siblings)
5 siblings, 2 replies; 13+ messages in thread
From: Christoph Hellwig @ 2020-04-08 15:27 UTC (permalink / raw)
To: x86, Dave Hansen, Andy Lutomirski, Peter Zijlstra, linux-kernel
Make use of lower level helpers that operate on the raw protection
values to make the code a little easier to understand, and to also
avoid extra conversions in a few callers.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/x86/include/asm/pgtable_types.h | 26 +++++++++++++-------------
arch/x86/mm/init_64.c | 2 +-
arch/x86/mm/pgtable.c | 8 ++------
3 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 75fe903124f8..a3b78d84b26a 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -488,24 +488,24 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
return __pgprot(cachemode2protval(pcm));
}
-static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+static inline unsigned long protval_4k_2_large(unsigned long val)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+}
+static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+{
+ return __pgprot(protval_4k_2_large(pgprot_val(pgprot)));
+}
+static inline unsigned long protval_large_2_4k(unsigned long val)
+{
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ ((val & _PAGE_PAT_LARGE) >>
+ (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
}
static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
- ((val & _PAGE_PAT_LARGE) >>
- (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+ return __pgprot(protval_large_2_4k(pgprot_val(pgprot)));
}
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 0a14711d3a93..3420377c7fd9 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -367,7 +367,7 @@ static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
pgprot_t prot;
pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
- pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
+ protval_4k_2_large(cachemode2protval(cache));
BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
pgd = pgd_offset_k((unsigned long)__va(phys));
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 7bd2c3a52297..edf9cea4871f 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -706,11 +706,9 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
if (pud_present(*pud) && !pud_huge(*pud))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pud, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot) | _PAGE_PSE))));
return 1;
}
@@ -738,11 +736,9 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
if (pmd_present(*pmd) && !pmd_huge(*pmd))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pmd, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot)) | _PAGE_PSE)));
return 1;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k()
2020-04-08 15:27 ` [PATCH 3/4] x86/mm: Cleanup pgprot_4k_2_large and pgprot_large_2_4k Christoph Hellwig
@ 2020-04-20 13:30 ` tip-bot2 for Christoph Hellwig
2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
1 sibling, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-20 13:30 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: 9e294786c89ae0904932c06d79e5e1c044864f65
Gitweb: https://git.kernel.org/tip/9e294786c89ae0904932c06d79e5e1c044864f65
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:44 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 20 Apr 2020 12:39:22 +02:00
x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k()
Make use of lower level helpers that operate on the raw protection
values to make the code a little easier to understand, and to also
avoid extra conversions in a few callers.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-4-hch@lst.de
---
arch/x86/include/asm/pgtable_types.h | 26 +++++++++++++-------------
arch/x86/mm/init_64.c | 2 +-
arch/x86/mm/pgtable.c | 8 ++------
3 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 75fe903..a3b78d8 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -488,24 +488,24 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
return __pgprot(cachemode2protval(pcm));
}
-static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+static inline unsigned long protval_4k_2_large(unsigned long val)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+}
+static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+{
+ return __pgprot(protval_4k_2_large(pgprot_val(pgprot)));
+}
+static inline unsigned long protval_large_2_4k(unsigned long val)
+{
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ ((val & _PAGE_PAT_LARGE) >>
+ (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
}
static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
- ((val & _PAGE_PAT_LARGE) >>
- (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+ return __pgprot(protval_large_2_4k(pgprot_val(pgprot)));
}
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 3b289c2..9a497ba 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -367,7 +367,7 @@ static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
pgprot_t prot;
pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
- pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
+ protval_4k_2_large(cachemode2protval(cache));
BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
pgd = pgd_offset_k((unsigned long)__va(phys));
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 7bd2c3a..edf9cea 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -706,11 +706,9 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
if (pud_present(*pud) && !pud_huge(*pud))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pud, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot) | _PAGE_PSE))));
return 1;
}
@@ -738,11 +736,9 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
if (pmd_present(*pmd) && !pmd_huge(*pmd))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pmd, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot)) | _PAGE_PSE)));
return 1;
}
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k()
2020-04-08 15:27 ` [PATCH 3/4] x86/mm: Cleanup pgprot_4k_2_large and pgprot_large_2_4k Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k() tip-bot2 for Christoph Hellwig
@ 2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
1 sibling, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-23 12:26 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: d073569363d9f076a568ce8c31250d332ccf33ce
Gitweb: https://git.kernel.org/tip/d073569363d9f076a568ce8c31250d332ccf33ce
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:44 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Thu, 23 Apr 2020 11:31:52 +02:00
x86/mm: Cleanup pgprot_4k_2_large() and pgprot_large_2_4k()
Make use of lower level helpers that operate on the raw protection
values to make the code a little easier to understand, and to also
avoid extra conversions in a few callers.
[ Qian: Fix a wrongly placed bracket in the original submission.
Reported and fixed by Qian Cai <cai@lca.pw>. Details in second
Link: below. ]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-4-hch@lst.de
Link: https://lkml.kernel.org/r/1ED37D02-125F-4919-861A-371981581D9E@lca.pw
---
arch/x86/include/asm/pgtable_types.h | 26 +++++++++++++-------------
arch/x86/mm/init_64.c | 2 +-
arch/x86/mm/pgtable.c | 8 ++------
3 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 75fe903..a3b78d8 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -488,24 +488,24 @@ static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
return __pgprot(cachemode2protval(pcm));
}
-static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+static inline unsigned long protval_4k_2_large(unsigned long val)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+}
+static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+{
+ return __pgprot(protval_4k_2_large(pgprot_val(pgprot)));
+}
+static inline unsigned long protval_large_2_4k(unsigned long val)
+{
+ return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+ ((val & _PAGE_PAT_LARGE) >>
+ (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
}
static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
{
- pgprotval_t val = pgprot_val(pgprot);
- pgprot_t new;
-
- pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
- ((val & _PAGE_PAT_LARGE) >>
- (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
- return new;
+ return __pgprot(protval_large_2_4k(pgprot_val(pgprot)));
}
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 3b289c2..9a497ba 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -367,7 +367,7 @@ static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
pgprot_t prot;
pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
- pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
+ protval_4k_2_large(cachemode2protval(cache));
BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
pgd = pgd_offset_k((unsigned long)__va(phys));
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 7bd2c3a..c54d1d0 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -706,11 +706,9 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
if (pud_present(*pud) && !pud_huge(*pud))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pud, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot)) | _PAGE_PSE)));
return 1;
}
@@ -738,11 +736,9 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
if (pmd_present(*pmd) && !pmd_huge(*pmd))
return 0;
- prot = pgprot_4k_2_large(prot);
-
set_pte((pte_t *)pmd, pfn_pte(
(u64)addr >> PAGE_SHIFT,
- __pgprot(pgprot_val(prot) | _PAGE_PSE)));
+ __pgprot(protval_4k_2_large(pgprot_val(prot)) | _PAGE_PSE)));
return 1;
}
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/4] x86/mm: Unexport __cachemode2pte_tbl
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
` (2 preceding siblings ...)
2020-04-08 15:27 ` [PATCH 3/4] x86/mm: Cleanup pgprot_4k_2_large and pgprot_large_2_4k Christoph Hellwig
@ 2020-04-08 15:27 ` Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] " tip-bot2 for Christoph Hellwig
2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
2020-04-20 8:46 ` hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
2020-04-20 10:30 ` Peter Zijlstra
5 siblings, 2 replies; 13+ messages in thread
From: Christoph Hellwig @ 2020-04-08 15:27 UTC (permalink / raw)
To: x86, Dave Hansen, Andy Lutomirski, Peter Zijlstra, linux-kernel
Exporting the raw data for a table is generally a bad idea. Move
cachemode2protval out of line given that it isn't really used in the
fast path, and then mark __cachemode2pte_tbl static.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/x86/include/asm/pgtable_types.h | 14 ++------------
arch/x86/mm/init.c | 11 +++++++++--
arch/x86/mm/pat/set_memory.c | 5 +++++
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index a3b78d84b26a..567abdbd64d3 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -467,8 +467,6 @@ static inline pteval_t pte_flags(pte_t pte)
return native_pte_val(pte) & PTE_FLAGS_MASK;
}
-extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
-
#define __pte2cm_idx(cb) \
((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
(((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
@@ -478,16 +476,8 @@ extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
(((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
(((i) & 1) << _PAGE_BIT_PWT))
-static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
-{
- if (likely(pcm == 0))
- return 0;
- return __cachemode2pte_tbl[pcm];
-}
-static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
-{
- return __pgprot(cachemode2protval(pcm));
-}
+unsigned long cachemode2protval(enum page_cache_mode pcm);
+
static inline unsigned long protval_4k_2_large(unsigned long val)
{
return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 8482ee51b225..4a8d0d67e729 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -49,7 +49,7 @@
* Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
* (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
*/
-uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
+static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
[_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
@@ -57,7 +57,14 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
};
-EXPORT_SYMBOL(__cachemode2pte_tbl);
+
+unsigned long cachemode2protval(enum page_cache_mode pcm)
+{
+ if (likely(pcm == 0))
+ return 0;
+ return __cachemode2pte_tbl[pcm];
+}
+EXPORT_SYMBOL(cachemode2protval);
static uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 6d5424069e2b..b8ee3f4e8202 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -68,6 +68,11 @@ static DEFINE_SPINLOCK(cpa_lock);
#define CPA_PAGES_ARRAY 4
#define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */
+static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
+{
+ return __pgprot(cachemode2protval(pcm));
+}
+
#ifdef CONFIG_PROC_FS
static unsigned long direct_pages_count[PG_LEVEL_NUM];
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Unexport __cachemode2pte_tbl
2020-04-08 15:27 ` [PATCH 4/4] x86/mm: Unexport __cachemode2pte_tbl Christoph Hellwig
@ 2020-04-20 13:30 ` tip-bot2 for Christoph Hellwig
2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
1 sibling, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-20 13:30 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: a85573f7e74191e5f5500c45fb4ec79cdfe13a08
Gitweb: https://git.kernel.org/tip/a85573f7e74191e5f5500c45fb4ec79cdfe13a08
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:45 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 20 Apr 2020 12:39:31 +02:00
x86/mm: Unexport __cachemode2pte_tbl
Exporting the raw data for a table is generally a bad idea. Move
cachemode2protval() out of line given that it isn't really used in the
fast path, and then mark __cachemode2pte_tbl static.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-5-hch@lst.de
---
arch/x86/include/asm/pgtable_types.h | 14 ++------------
arch/x86/mm/init.c | 11 +++++++++--
arch/x86/mm/pat/set_memory.c | 5 +++++
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index a3b78d8..567abdb 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -467,8 +467,6 @@ static inline pteval_t pte_flags(pte_t pte)
return native_pte_val(pte) & PTE_FLAGS_MASK;
}
-extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
-
#define __pte2cm_idx(cb) \
((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
(((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
@@ -478,16 +476,8 @@ extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
(((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
(((i) & 1) << _PAGE_BIT_PWT))
-static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
-{
- if (likely(pcm == 0))
- return 0;
- return __cachemode2pte_tbl[pcm];
-}
-static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
-{
- return __pgprot(cachemode2protval(pcm));
-}
+unsigned long cachemode2protval(enum page_cache_mode pcm);
+
static inline unsigned long protval_4k_2_large(unsigned long val)
{
return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 4a55d68..71720dd 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -49,7 +49,7 @@
* Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
* (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
*/
-uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
+static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
[_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
@@ -57,7 +57,14 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
};
-EXPORT_SYMBOL(__cachemode2pte_tbl);
+
+unsigned long cachemode2protval(enum page_cache_mode pcm)
+{
+ if (likely(pcm == 0))
+ return 0;
+ return __cachemode2pte_tbl[pcm];
+}
+EXPORT_SYMBOL(cachemode2protval);
static uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 59eca6a..a28f0c3 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -68,6 +68,11 @@ static DEFINE_SPINLOCK(cpa_lock);
#define CPA_PAGES_ARRAY 4
#define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */
+static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
+{
+ return __pgprot(cachemode2protval(pcm));
+}
+
#ifdef CONFIG_PROC_FS
static unsigned long direct_pages_count[PG_LEVEL_NUM];
^ permalink raw reply related [flat|nested] 13+ messages in thread* [tip: x86/mm] x86/mm: Unexport __cachemode2pte_tbl
2020-04-08 15:27 ` [PATCH 4/4] x86/mm: Unexport __cachemode2pte_tbl Christoph Hellwig
2020-04-20 13:30 ` [tip: x86/mm] " tip-bot2 for Christoph Hellwig
@ 2020-04-23 12:26 ` tip-bot2 for Christoph Hellwig
1 sibling, 0 replies; 13+ messages in thread
From: tip-bot2 for Christoph Hellwig @ 2020-04-23 12:26 UTC (permalink / raw)
To: linux-tip-commits
Cc: Christoph Hellwig, Borislav Petkov, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the x86/mm branch of tip:
Commit-ID: de17a37896e1ad9e17ebd5274a50c33e18c9cb90
Gitweb: https://git.kernel.org/tip/de17a37896e1ad9e17ebd5274a50c33e18c9cb90
Author: Christoph Hellwig <hch@lst.de>
AuthorDate: Wed, 08 Apr 2020 17:27:45 +02:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Thu, 23 Apr 2020 11:34:31 +02:00
x86/mm: Unexport __cachemode2pte_tbl
Exporting the raw data for a table is generally a bad idea. Move
cachemode2protval() out of line given that it isn't really used in the
fast path, and then mark __cachemode2pte_tbl static.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-5-hch@lst.de
---
arch/x86/include/asm/pgtable_types.h | 14 ++------------
arch/x86/mm/init.c | 11 +++++++++--
arch/x86/mm/pat/set_memory.c | 5 +++++
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index a3b78d8..567abdb 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -467,8 +467,6 @@ static inline pteval_t pte_flags(pte_t pte)
return native_pte_val(pte) & PTE_FLAGS_MASK;
}
-extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
-
#define __pte2cm_idx(cb) \
((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
(((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
@@ -478,16 +476,8 @@ extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
(((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
(((i) & 1) << _PAGE_BIT_PWT))
-static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
-{
- if (likely(pcm == 0))
- return 0;
- return __cachemode2pte_tbl[pcm];
-}
-static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
-{
- return __pgprot(cachemode2protval(pcm));
-}
+unsigned long cachemode2protval(enum page_cache_mode pcm);
+
static inline unsigned long protval_4k_2_large(unsigned long val)
{
return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 4a55d68..71720dd 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -49,7 +49,7 @@
* Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
* (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
*/
-uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
+static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
[_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
@@ -57,7 +57,14 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
[_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
};
-EXPORT_SYMBOL(__cachemode2pte_tbl);
+
+unsigned long cachemode2protval(enum page_cache_mode pcm)
+{
+ if (likely(pcm == 0))
+ return 0;
+ return __cachemode2pte_tbl[pcm];
+}
+EXPORT_SYMBOL(cachemode2protval);
static uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 59eca6a..a28f0c3 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -68,6 +68,11 @@ static DEFINE_SPINLOCK(cpa_lock);
#define CPA_PAGES_ARRAY 4
#define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */
+static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
+{
+ return __pgprot(cachemode2protval(pcm));
+}
+
#ifdef CONFIG_PROC_FS
static unsigned long direct_pages_count[PG_LEVEL_NUM];
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: hide __pte2cachemode_tbl and __cachemode2pte_tbl
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
` (3 preceding siblings ...)
2020-04-08 15:27 ` [PATCH 4/4] x86/mm: Unexport __cachemode2pte_tbl Christoph Hellwig
@ 2020-04-20 8:46 ` Christoph Hellwig
2020-04-20 10:30 ` Peter Zijlstra
5 siblings, 0 replies; 13+ messages in thread
From: Christoph Hellwig @ 2020-04-20 8:46 UTC (permalink / raw)
To: x86, Dave Hansen, Andy Lutomirski, Peter Zijlstra, linux-kernel
On Wed, Apr 08, 2020 at 05:27:41PM +0200, Christoph Hellwig wrote:
> Hi all,
>
> this series avoids pointlessly exposing the cachemode to pte bit
> translation tables to modules.
Any comments?
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: hide __pte2cachemode_tbl and __cachemode2pte_tbl
2020-04-08 15:27 hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
` (4 preceding siblings ...)
2020-04-20 8:46 ` hide __pte2cachemode_tbl and __cachemode2pte_tbl Christoph Hellwig
@ 2020-04-20 10:30 ` Peter Zijlstra
5 siblings, 0 replies; 13+ messages in thread
From: Peter Zijlstra @ 2020-04-20 10:30 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: x86, Dave Hansen, Andy Lutomirski, linux-kernel
On Wed, Apr 08, 2020 at 05:27:41PM +0200, Christoph Hellwig wrote:
> Hi all,
>
> this series avoids pointlessly exposing the cachemode to pte bit
> translation tables to modules.
Nice!
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
^ permalink raw reply [flat|nested] 13+ messages in thread