* [PATCH v5 1/9] arm64: dts: allwinner: h6: Add clock to CPU cores
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map Clément Péron
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Yangtao Li, Clément Péron
From: Yangtao Li <tiny.windzz@gmail.com>
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a5ee68388bd3..370e77b86fe1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -25,6 +25,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu1: cpu@1 {
@@ -32,6 +34,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu2: cpu@2 {
@@ -39,6 +43,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu3: cpu@3 {
@@ -46,6 +52,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
2020-04-20 13:00 ` [PATCH v5 1/9] arm64: dts: allwinner: h6: Add clock to CPU cores Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:46 ` Ondřej Jirman
2020-04-20 13:00 ` [PATCH v5 3/9] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Clément Péron
` (7 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Ondrej Jirman, Clément Péron
From: Ondrej Jirman <megous@megous.com>
This enables passive cooling by down-regulating CPU voltage
and frequency.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 370e77b86fe1..60da1627772b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -964,6 +964,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpu-thermal {
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map
2020-04-20 13:00 ` [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map Clément Péron
@ 2020-04-20 13:46 ` Ondřej Jirman
2020-04-20 14:20 ` Clément Péron
0 siblings, 1 reply; 13+ messages in thread
From: Ondřej Jirman @ 2020-04-20 13:46 UTC (permalink / raw)
To: Clément Péron
Cc: Maxime Ripard, Chen-Yu Tsai, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
Hi,
On Mon, Apr 20, 2020 at 03:00:14PM +0200, Clément Péron wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> This enables passive cooling by down-regulating CPU voltage
> and frequency.
Does this not produce a lot of warnings for you during compilation?
regards,
o.
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 370e77b86fe1..60da1627772b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -964,6 +964,30 @@
> polling-delay-passive = <0>;
> polling-delay = <0>;
> thermal-sensors = <&ths 0>;
> +
> + trips {
> + cpu_alert: cpu-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu-crit {
> + temperature = <100000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> gpu-thermal {
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map
2020-04-20 13:46 ` Ondřej Jirman
@ 2020-04-20 14:20 ` Clément Péron
0 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 14:20 UTC (permalink / raw)
To: Ondřej Jirman, Clément Péron, Maxime Ripard,
Chen-Yu Tsai, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel, linux-sunxi
Hi Ondrej,
On Mon, 20 Apr 2020 at 15:46, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi,
>
> On Mon, Apr 20, 2020 at 03:00:14PM +0200, Clément Péron wrote:
> > From: Ondrej Jirman <megous@megous.com>
> >
> > This enables passive cooling by down-regulating CPU voltage
> > and frequency.
>
> Does this not produce a lot of warnings for you during compilation?
I got flooded by lots of warnings, from sun50i-a64, stringray-usb,
ipq6018 and didn't see but two are from sun50i-h6.
The #cooling-cells property is missing for CPU.
Will send a patch for noticing.
Regard,
Clement
>
> regards,
> o.
>
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 370e77b86fe1..60da1627772b 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -964,6 +964,30 @@
> > polling-delay-passive = <0>;
> > polling-delay = <0>;
> > thermal-sensors = <&ths 0>;
> > +
> > + trips {
> > + cpu_alert: cpu-alert {
> > + temperature = <85000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + cpu-crit {
> > + temperature = <100000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert>;
> > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > };
> >
> > gpu-thermal {
> > --
> > 2.20.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 3/9] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
2020-04-20 13:00 ` [PATCH v5 1/9] arm64: dts: allwinner: h6: Add clock to CPU cores Clément Péron
2020-04-20 13:00 ` [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 4/9] arm64: configs: Enable sun50i cpufreq nvmem Clément Péron
` (6 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Ondrej Jirman, Clément Péron
From: Ondrej Jirman <megous@megous.com>
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..9ebd97b04b1a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1608000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x4>;
+ };
};
watchdog: watchdog@30090a0 {
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 4/9] arm64: configs: Enable sun50i cpufreq nvmem
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (2 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 3/9] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 5/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1 Clément Péron
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.
Enable this option in arm64 defconfig.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f9eefb5940ca..37e512c135ba 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -84,6 +84,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_IMX_CPUFREQ_DT=m
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 5/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (3 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 4/9] arm64: configs: Enable sun50i cpufreq nvmem Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 6/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3 Clément Péron
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Enable CPU opp tables for Beelink GS1.
This needs to change the CPU regulator max voltage to fit
the OPP table.
Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.
There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 8f09d209359b..3f7ceeb1a767 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -77,6 +78,10 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdca>;
+};
+
&de {
status = "okay";
};
@@ -234,7 +239,8 @@
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};
@@ -242,6 +248,7 @@
regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-gpu";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 6/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (4 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 5/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1 Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 7/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6 Clément Péron
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Enable CPU opp tables for Orange Pi 3.
This needs to change the CPU regulator max voltage to fit
the OPP table.
Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.
There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 47f579610dcc..15c9dd8c4479 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -257,6 +258,7 @@
regulator-always-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};
@@ -264,6 +266,7 @@
regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-gpu";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 7/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (5 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 6/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3 Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 8/9] arm64: dts: allwinner: Sort Pine H64 device-tree nodes Clément Péron
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Enable CPU opp tables for Tanix TX6.
Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.
This voltage has been found using a voltmeter and could be wrong.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
index 83e6cb0e59ce..be81330db14f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -37,6 +38,17 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_vdd_cpu_gpu: vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpu_gpu>;
};
&de {
@@ -56,6 +68,7 @@
};
&gpu {
+ mali-supply = <®_vdd_cpu_gpu>;
status = "okay";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 8/9] arm64: dts: allwinner: Sort Pine H64 device-tree nodes
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (6 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 7/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6 Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:00 ` [PATCH v5 9/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64 Clément Péron
2020-04-20 13:25 ` [PATCH v5 0/9] Add support for Allwinner H6 DVFS Maxime Ripard
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Pine H64 device-tree have some nodes not properly sorted.
Fix this.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b0642d841933..63a785b534e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -80,6 +80,18 @@
};
};
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
&emac {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -91,17 +103,6 @@
status = "okay";
};
-&mdio {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-&de {
- status = "okay";
-};
-
&gpu {
mali-supply = <®_dcdcc>;
status = "okay";
@@ -117,12 +118,11 @@
};
};
-&ehci0 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
&mmc0 {
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 9/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (7 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 8/9] arm64: dts: allwinner: Sort Pine H64 device-tree nodes Clément Péron
@ 2020-04-20 13:00 ` Clément Péron
2020-04-20 13:25 ` [PATCH v5 0/9] Add support for Allwinner H6 DVFS Maxime Ripard
9 siblings, 0 replies; 13+ messages in thread
From: Clément Péron @ 2020-04-20 13:00 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi,
Clément Péron
Enable CPU and GPU opp tables for Pine H64.
This needs to change the CPU regulator max voltage to fit
the OPP table.
Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.
There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 63a785b534e1..af85b2074867 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -80,6 +81,10 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdca>;
+};
+
&de {
status = "okay";
};
@@ -238,7 +243,8 @@
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};
@@ -246,6 +252,7 @@
regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-gpu";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 0/9] Add support for Allwinner H6 DVFS
2020-04-20 13:00 [PATCH v5 0/9] Add support for Allwinner H6 DVFS Clément Péron
` (8 preceding siblings ...)
2020-04-20 13:00 ` [PATCH v5 9/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64 Clément Péron
@ 2020-04-20 13:25 ` Maxime Ripard
9 siblings, 0 replies; 13+ messages in thread
From: Maxime Ripard @ 2020-04-20 13:25 UTC (permalink / raw)
To: Clément Péron
Cc: Chen-Yu Tsai, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 296 bytes --]
On Mon, Apr 20, 2020 at 03:00:12PM +0200, Clément Péron wrote:
> Hi,
>
> This is the same as v4 and v3 on top.
> I have also fix the commit title for Pine H64 as we now only enable CPU DVFS.
>
> Sorry for the noise,
> Clément
I dropped the previous ones and applied, thanks!
Maxime
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 13+ messages in thread