From: Kamal Dasu <kdasu.kdev@gmail.com>
To: Kamal Dasu <kdasu.kdev@gmail.com>,
bcm-kernel-feedback-list@broadcom.com,
Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [Patch v3 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds
Date: Mon, 20 Apr 2020 15:08:51 -0400 [thread overview]
Message-ID: <20200420190853.45614-8-kdasu.kdev@gmail.com> (raw)
In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com>
Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of
1-7, while the default value prohibits these values and requires a minimum
clock divider value of 8.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index a3936ae5a860..edc601dbf221 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -107,13 +107,15 @@
#define MSPI_SPCR2_SPE BIT(6)
#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
+#define MSPI_SPCR3_FASTBR BIT(0)
+#define MSPI_SPCR3_FASTDT BIT(1)
+
#define MSPI_MSPI_STATUS_SPIF BIT(0)
#define INTR_BASE_BIT_SHIFT 0x02
#define INTR_COUNT 0x07
#define NUM_CHIPSELECT 4
-#define QSPI_SPBR_MIN 8U
#define QSPI_SPBR_MAX 255U
#define OPCODE_DIOR 0xBB
@@ -227,6 +229,25 @@ static inline bool has_bspi(struct bcm_qspi *qspi)
return qspi->bspi_mode;
}
+/* hardware supports spcr3 and fast baud-rate */
+static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
+{
+ if (!has_bspi(qspi) &&
+ ((qspi->mspi_maj_rev >= 1) &&
+ (qspi->mspi_min_rev >= 5)))
+ return true;
+
+ return false;
+}
+
+static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
+{
+ if (bcm_qspi_has_fastbr(qspi))
+ return 1;
+ else
+ return 8;
+}
+
/* Read qspi controller register*/
static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
unsigned int offset)
@@ -534,7 +555,7 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
if (xp->speed_hz)
spbr = qspi->base_clk / (2 * xp->speed_hz);
- spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
+ spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
spcr = MSPI_MASTER_BIT;
@@ -544,6 +565,14 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
spcr |= xp->mode & 3;
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
+ if (bcm_qspi_has_fastbr(qspi)) {
+ spcr = 0;
+
+ /* enable fastbr */
+ spcr |= MSPI_SPCR3_FASTBR;
+ bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
+ }
+
qspi->last_parms = *xp;
}
@@ -1388,7 +1417,6 @@ int bcm_qspi_probe(struct platform_device *pdev,
}
qspi->base_clk = clk_get_rate(qspi->clk);
- qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
if (data->has_mspi_rev) {
rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
@@ -1400,6 +1428,8 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->mspi_maj_rev = (rev >> 4) & 0xf;
qspi->mspi_min_rev = rev & 0xf;
+ qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
+
bcm_qspi_hw_init(qspi);
init_completion(&qspi->mspi_done);
init_completion(&qspi->bspi_done);
--
2.17.1
next prev parent reply other threads:[~2020-04-20 19:09 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200420190853.45614-1-kdasu.kdev@gmail.com>
2020-04-20 19:08 ` [Patch v3 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-21 15:06 ` Mark Brown
2020-04-21 17:11 ` Florian Fainelli
2020-04-21 17:15 ` Mark Brown
2020-04-21 17:17 ` Florian Fainelli
2020-04-21 17:20 ` Mark Brown
2020-04-21 18:31 ` Konstantin Ryabitsev
2020-04-21 18:54 ` Mark Brown
2020-04-20 19:08 ` [Patch v3 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
2020-04-20 19:08 ` [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
2020-04-20 19:08 ` [Patch v3 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
2020-04-20 19:08 ` [Patch v3 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
2020-04-20 19:08 ` [Patch v3 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
2020-04-20 19:08 ` Kamal Dasu [this message]
2020-04-20 19:08 ` [Patch v3 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-20 19:08 ` [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
2020-04-21 12:50 ` Mark Brown
2020-04-21 14:53 ` Kamal Dasu
2020-04-21 14:59 ` Mark Brown
2020-04-21 18:19 ` Kamal Dasu
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