* [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example
@ 2020-04-14 13:24 peng.fan
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: peng.fan @ 2020-04-14 13:24 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, jaswinder.singh, linux
Cc: kernel, festevam, linux-imx, Anson.Huang, linux-arm-kernel,
linux-kernel, devicetree, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The example use i.MX8QXP MU, but actually the MU is compatible with
i.MX6SX, so add the compatible.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
index 31486c9f6443..26b7a88c2fea 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
@@ -51,7 +51,7 @@ Optional properties:
Examples:
--------
lsio_mu0: mailbox@5d1b0000 {
- compatible = "fsl,imx8qxp-mu";
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x0 0x5d1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
--
2.16.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel
2020-04-14 13:24 [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example peng.fan
@ 2020-04-14 13:24 ` peng.fan
2020-04-15 5:50 ` Oleksij Rempel
2020-04-28 8:50 ` Shawn Guo
2020-04-15 5:49 ` [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example Oleksij Rempel
2020-04-20 21:07 ` Rob Herring
2 siblings, 2 replies; 6+ messages in thread
From: peng.fan @ 2020-04-14 13:24 UTC (permalink / raw)
To: shawnguo, s.hauer, robh+dt, jaswinder.singh, linux
Cc: kernel, festevam, linux-imx, Anson.Huang, linux-arm-kernel,
linux-kernel, devicetree, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
With mailbox driver support i.MX8 SCU MU channel, we could
use it to avoid trigger interrupts for each TR/RR registers
in one MU, instead, only one RX interrupt for a recv and
one TX interrupt for a send.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Note:
This patch needs https://patchwork.kernel.org/patch/11446659/
The other three patches in the patchset has been in linux-next
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e8ffb7590656..d1c3c98e4b39 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -141,17 +141,11 @@
scu {
compatible = "fsl,imx-scu";
- mbox-names = "tx0", "tx1", "tx2", "tx3",
- "rx0", "rx1", "rx2", "rx3",
+ mbox-names = "tx0",
+ "rx0",
"gip3";
mboxes = <&lsio_mu1 0 0
- &lsio_mu1 0 1
- &lsio_mu1 0 2
- &lsio_mu1 0 3
&lsio_mu1 1 0
- &lsio_mu1 1 1
- &lsio_mu1 1 2
- &lsio_mu1 1 3
&lsio_mu1 3 3>;
clk: clock-controller {
@@ -548,14 +542,14 @@
};
lsio_mu1: mailbox@5d1c0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1c0000 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
lsio_mu2: mailbox@5d1d0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1d0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
@@ -563,7 +557,7 @@
};
lsio_mu3: mailbox@5d1e0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
@@ -571,7 +565,7 @@
};
lsio_mu4: mailbox@5d1f0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
--
2.16.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example
2020-04-14 13:24 [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example peng.fan
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
@ 2020-04-15 5:49 ` Oleksij Rempel
2020-04-20 21:07 ` Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Oleksij Rempel @ 2020-04-15 5:49 UTC (permalink / raw)
To: peng.fan
Cc: shawnguo, s.hauer, robh+dt, jaswinder.singh, linux, devicetree,
Anson.Huang, linux-kernel, linux-imx, kernel, festevam,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1385 bytes --]
On Tue, Apr 14, 2020 at 09:24:27PM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The example use i.MX8QXP MU, but actually the MU is compatible with
> i.MX6SX, so add the compatible.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> index 31486c9f6443..26b7a88c2fea 100644
> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> @@ -51,7 +51,7 @@ Optional properties:
> Examples:
> --------
> lsio_mu0: mailbox@5d1b0000 {
> - compatible = "fsl,imx8qxp-mu";
> + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> reg = <0x0 0x5d1b0000 0x0 0x10000>;
> interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> --
> 2.16.4
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
@ 2020-04-15 5:50 ` Oleksij Rempel
2020-04-28 8:50 ` Shawn Guo
1 sibling, 0 replies; 6+ messages in thread
From: Oleksij Rempel @ 2020-04-15 5:50 UTC (permalink / raw)
To: peng.fan
Cc: shawnguo, s.hauer, robh+dt, jaswinder.singh, linux, devicetree,
Anson.Huang, linux-kernel, linux-imx, kernel, festevam,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 3035 bytes --]
On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> With mailbox driver support i.MX8 SCU MU channel, we could
> use it to avoid trigger interrupts for each TR/RR registers
> in one MU, instead, only one RX interrupt for a recv and
> one TX interrupt for a send.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
>
> Note:
> This patch needs https://patchwork.kernel.org/patch/11446659/
> The other three patches in the patchset has been in linux-next
>
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index e8ffb7590656..d1c3c98e4b39 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -141,17 +141,11 @@
>
> scu {
> compatible = "fsl,imx-scu";
> - mbox-names = "tx0", "tx1", "tx2", "tx3",
> - "rx0", "rx1", "rx2", "rx3",
> + mbox-names = "tx0",
> + "rx0",
> "gip3";
> mboxes = <&lsio_mu1 0 0
> - &lsio_mu1 0 1
> - &lsio_mu1 0 2
> - &lsio_mu1 0 3
> &lsio_mu1 1 0
> - &lsio_mu1 1 1
> - &lsio_mu1 1 2
> - &lsio_mu1 1 3
> &lsio_mu1 3 3>;
>
> clk: clock-controller {
> @@ -548,14 +542,14 @@
> };
>
> lsio_mu1: mailbox@5d1c0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> reg = <0x5d1c0000 0x10000>;
> interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> };
>
> lsio_mu2: mailbox@5d1d0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> reg = <0x5d1d0000 0x10000>;
> interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> @@ -563,7 +557,7 @@
> };
>
> lsio_mu3: mailbox@5d1e0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> reg = <0x5d1e0000 0x10000>;
> interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> @@ -571,7 +565,7 @@
> };
>
> lsio_mu4: mailbox@5d1f0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> reg = <0x5d1f0000 0x10000>;
> interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> --
> 2.16.4
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example
2020-04-14 13:24 [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example peng.fan
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
2020-04-15 5:49 ` [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example Oleksij Rempel
@ 2020-04-20 21:07 ` Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-04-20 21:07 UTC (permalink / raw)
To: peng.fan
Cc: shawnguo, s.hauer, robh+dt, jaswinder.singh, linux, kernel,
festevam, linux-imx, Anson.Huang, linux-arm-kernel, linux-kernel,
devicetree, Peng Fan
On Tue, 14 Apr 2020 21:24:27 +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The example use i.MX8QXP MU, but actually the MU is compatible with
> i.MX6SX, so add the compatible.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied, thanks.
Rob
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
2020-04-15 5:50 ` Oleksij Rempel
@ 2020-04-28 8:50 ` Shawn Guo
1 sibling, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2020-04-28 8:50 UTC (permalink / raw)
To: peng.fan
Cc: s.hauer, robh+dt, jaswinder.singh, linux, kernel, festevam,
linux-imx, Anson.Huang, linux-arm-kernel, linux-kernel,
devicetree
On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> With mailbox driver support i.MX8 SCU MU channel, we could
> use it to avoid trigger interrupts for each TR/RR registers
> in one MU, instead, only one RX interrupt for a recv and
> one TX interrupt for a send.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-28 8:50 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-04-14 13:24 [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example peng.fan
2020-04-14 13:24 ` [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel peng.fan
2020-04-15 5:50 ` Oleksij Rempel
2020-04-28 8:50 ` Shawn Guo
2020-04-15 5:49 ` [PATCH 1/2] dt-bindings: mailbox: imx-mu: correct example Oleksij Rempel
2020-04-20 21:07 ` Rob Herring
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