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* [PATCH] spi: pxa2xx: Apply CS clk quirk to BXT
@ 2020-04-27 23:32 Evan Green
  2020-04-30 14:23 ` Mark Brown
  0 siblings, 1 reply; 2+ messages in thread
From: Evan Green @ 2020-04-27 23:32 UTC (permalink / raw)
  To: Mark Brown
  Cc: Evan Green, Shobhit Srivastava, Andy Shevchenko, Daniel Mack,
	Haojian Zhuang, Robert Jarzmik, linux-arm-kernel, linux-kernel,
	linux-spi

With a couple allies at Intel, and much badgering, I got confirmation
from Intel that at least BXT suffers from the same SPI chip-select
issue as Cannonlake (and beyond). The issue being that after going
through runtime suspend/resume, toggling the chip-select line without
also sending data does nothing.

Add the quirk to BXT to briefly toggle dynamic clock gating off and
on, forcing the fabric to wake up enough to notice the CS register
change.

Signed-off-by: Evan Green <evgreen@chromium.org>
Cc: Shobhit Srivastava <shobhit.srivastava@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---

I don't actually have a BXT (Broxton/Apollolake?) system to test this.
To be honest I suspect the issue is there in older generations as well,
but I couldn't get Intel to confirm that, so this seemed like the
only safe change.
---
 drivers/spi/spi-pxa2xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 73d2a65d0b6ef..20dcbd35611a7 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -150,6 +150,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.tx_threshold_hi = 48,
 		.cs_sel_shift = 8,
 		.cs_sel_mask = 3 << 8,
+		.cs_clk_stays_gated = true,
 	},
 	{	/* LPSS_CNL_SSP */
 		.offset = 0x200,
-- 
2.24.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] spi: pxa2xx: Apply CS clk quirk to BXT
  2020-04-27 23:32 [PATCH] spi: pxa2xx: Apply CS clk quirk to BXT Evan Green
@ 2020-04-30 14:23 ` Mark Brown
  0 siblings, 0 replies; 2+ messages in thread
From: Mark Brown @ 2020-04-30 14:23 UTC (permalink / raw)
  To: Evan Green
  Cc: Haojian Zhuang, Shobhit Srivastava, Robert Jarzmik, linux-spi,
	linux-kernel, Daniel Mack, Andy Shevchenko, linux-arm-kernel

On Mon, 27 Apr 2020 16:32:48 -0700, Evan Green wrote:
> With a couple allies at Intel, and much badgering, I got confirmation
> from Intel that at least BXT suffers from the same SPI chip-select
> issue as Cannonlake (and beyond). The issue being that after going
> through runtime suspend/resume, toggling the chip-select line without
> also sending data does nothing.
> 
> Add the quirk to BXT to briefly toggle dynamic clock gating off and
> on, forcing the fabric to wake up enough to notice the CS register
> change.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8

Thanks!

[1/1] spi: pxa2xx: Apply CS clk quirk to BXT
      commit: 6eefaee4f2d366a389da0eb95e524ba82bf358c4

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply	[flat|nested] 2+ messages in thread

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