linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Mark Brown <broonie@kernel.org>
Cc: Serge Semin <fancer.lancer@gmail.com>,
	Lars Povlsen <lars.povlsen@microchip.com>,
	SoC Team <soc@kernel.org>,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: Re: [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT
Date: Thu, 14 May 2020 16:04:07 +0300	[thread overview]
Message-ID: <20200514130407.guyk3r4ltjvszy5s@mobilestation> (raw)
In-Reply-To: <20200513142050.GH4803@sirena.org.uk>

Hi Mark

On Wed, May 13, 2020 at 03:20:50PM +0100, Mark Brown wrote:
> On Wed, May 13, 2020 at 04:00:22PM +0200, Lars Povlsen wrote:
> > With this change a SPI controller can be added without having a IRQ
> > associated, and causing all transfers to be polled. For SPI controllers
> > without DMA, this can significantly improve performance by less
> > interrupt handling overhead.
> 
> This overlaps substantially with some work that Serge Semin (CCed) has
> in progress, please coordinate with him.

Thanks for copying me these mails. I haven't been Cc'ed in the series and
hasn't been subscribed to the SPI mailing list, so I would have definitely
missed that.

I would like to coordinate my efforts with Lars. I'll have the patchset reviewed
soon in addition providing my comments/suggestions of how to make it useful for
both mine and Lars solution.

One thing I can tell about the mem_ops he implemented, is that they aren't
mem_ops, but dirmap (as you remember it's also implemented in my code, but with
alignment specific), and the exec_mem_op partly consists of a code, which belong
to the supports_op() callback. The rest of my comments will be inlined in the
patches.

-Sergey

  parent reply	other threads:[~2020-05-14 13:04 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 14:00 [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 14:00 ` [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Lars Povlsen
2020-05-13 14:55   ` Andy Shevchenko
2020-05-19 10:25     ` Lars Povlsen
     [not found]   ` <20200513142050.GH4803@sirena.org.uk>
2020-05-14 13:04     ` Serge Semin [this message]
2020-05-15  9:11       ` Lars Povlsen
     [not found]   ` <20200513143753.GI4803@sirena.org.uk>
2020-05-19 10:21     ` Lars Povlsen
2020-06-02 19:10   ` Serge Semin
2020-06-09  9:13     ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 02/10] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-06-02 19:39   ` Serge Semin
2020-06-09 10:04     ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 03/10] spi: dw: Add support for client driver memory operations Lars Povlsen
2020-05-13 14:00 ` [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Lars Povlsen
     [not found]   ` <20200513145213.GJ4803@sirena.org.uk>
2020-05-19 11:47     ` Lars Povlsen
     [not found]       ` <20200519115829.GI4611@sirena.org.uk>
2020-05-19 12:10         ` Lars Povlsen
2020-06-02 19:49   ` Serge Semin
2020-06-09 10:27     ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Lars Povlsen
     [not found]   ` <20200513151811.GL4803@sirena.org.uk>
2020-05-19 12:05     ` Lars Povlsen
2020-06-02 21:12       ` Serge Semin
2020-06-10 14:28         ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Lars Povlsen
2020-06-02 23:07   ` Serge Semin
2020-06-10 12:27     ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 07/10] " Lars Povlsen
     [not found]   ` <20200514102516.GD5127@sirena.org.uk>
2020-05-19  9:29     ` Lars Povlsen
2020-06-02 23:22   ` Serge Semin
2020-05-13 14:00 ` [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Lars Povlsen
2020-05-13 14:00 ` [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-05-13 14:00 ` [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen
2020-05-29 16:21 ` [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Serge Semin
2020-06-02  8:18   ` Lars Povlsen
2020-06-02  8:21     ` Serge Semin
2020-06-02 23:44     ` Serge Semin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200514130407.guyk3r4ltjvszy5s@mobilestation \
    --to=sergey.semin@baikalelectronics.ru \
    --cc=UNGLinuxDriver@microchip.com \
    --cc=alexandre.belloni@bootlin.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=broonie@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=lars.povlsen@microchip.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-spi@vger.kernel.org \
    --cc=soc@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).