From: Lars Povlsen <lars.povlsen@microchip.com>
To: Mark Brown <broonie@kernel.org>
Cc: SoC Team <soc@kernel.org>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH 07/10] spi: spi-dw-mchp: Add Sparx5 support
Date: Tue, 19 May 2020 11:29:17 +0200 [thread overview]
Message-ID: <20200519092917.GB24801@soft-dev15.microsemi.net> (raw)
In-Reply-To: <20200514102516.GD5127@sirena.org.uk>
[Sorry about the slight delay on getting back on this]
On 14/05/20 11:25, Mark Brown wrote:
> Date: Thu, 14 May 2020 11:25:16 +0100
> From: Mark Brown <broonie@kernel.org>
> To: Lars Povlsen <lars.povlsen@microchip.com>
> Cc: SoC Team <soc@kernel.org>, Microchip Linux Driver Support
> <UNGLinuxDriver@microchip.com>, linux-spi@vger.kernel.org,
> devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
> linux-arm-kernel@lists.infradead.org, Alexandre Belloni
> <alexandre.belloni@bootlin.com>
> Subject: Re: [PATCH 07/10] spi: spi-dw-mchp: Add Sparx5 support
> User-Agent: Mutt/1.10.1 (2018-07-13)
>
> On Wed, May 13, 2020 at 04:00:28PM +0200, Lars Povlsen wrote:
>
> > +static void dw_spi_mchp_set_cs_owner(struct dw_spi_mchp *dwsmchp,
> > + const struct dw_spi_mchp_props *props,
> > + u8 cs, u8 owner)
> > {
> > + u8 dummy = (owner == MSCC_IF_SI_OWNER_SIBM ?
> > + MSCC_IF_SI_OWNER_SIMC : MSCC_IF_SI_OWNER_SIBM);
>
> Please write normal conditional statements to improve legibility.
>
I will take your recommendation to heart.
> > +static void dw_spi_mchp_set_cs(struct spi_device *spi, bool nEnable)
> > +{
> > + bool enable = !nEnable; /* This keeps changing in the API... */
>
> No, it doesn't. The API has not changed for more than a decade.
>
I will remove the comment.
I think the comment was related to when we got bitten by the below
change, but alas.
commit ada9e3fcc175db4538f5b5e05abf5dedf626e550
Author: Charles Keepax <ckeepax@opensource.cirrus.com>
Date: Wed Nov 27 15:39:36 2019 +0000
spi: dw: Correct handling of native chipselect
This patch reverts commit 6e0a32d6f376 ("spi: dw: Fix default polarity
of native chipselect").
> > + } else if (props->ss_force_ena_off) {
> > + if (enable) {
> > + /* Ensure CS toggles, so start off all disabled */
> > + regmap_write(dwsmchp->syscon, props->ss_force_val_off,
> > + ~0);
>
> What's all this force_ena_off stuff about? The controller should not be
> making decisions about management of the chip select, this will break
> users.
>
Our controller is not using DMA, but the FIFO interface. And as the DW
controller drops CS when the FIFO runs empty, this will upset SPI
devices. The "ss_force" is something the HW designes put on top to
"override" the CS. We could of course use the GPIO's specifically to
overcome this - but the "boot" CS 0 is a builtin CS, with no
underlying GPIO.
Add to this that the HW dept decided to add *2* physical SPI busses to
the same controller. That we also need to switch between. And ensure
CS gets dropped correctly before changing tracks...
Long story, lot of grief...
> > + if (pdev->dev.of_node) {
> > + int i;
> > +
> > + for (i = 0; i < dws->num_cs; i++) {
> > + int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
> > + "cs-gpios", i);
> > +
> > + if (cs_gpio == -EPROBE_DEFER) {
> > + ret = cs_gpio;
> > + goto out;
> > + }
> > +
> > + if (gpio_is_valid(cs_gpio)) {
> > + ret = devm_gpio_request(&pdev->dev, cs_gpio,
> > + dev_name(&pdev->dev));
> > + if (ret)
> > + goto out;
>
> Set use_gpio_descriptors and let the core manage the GPIO.
Good suggestion, just the ticket!
And thank you very much for your time & comments.
---Lars
next prev parent reply other threads:[~2020-05-19 9:29 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 14:00 [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 14:00 ` [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Lars Povlsen
2020-05-13 14:55 ` Andy Shevchenko
2020-05-19 10:25 ` Lars Povlsen
[not found] ` <20200513142050.GH4803@sirena.org.uk>
2020-05-14 13:04 ` Serge Semin
2020-05-15 9:11 ` Lars Povlsen
[not found] ` <20200513143753.GI4803@sirena.org.uk>
2020-05-19 10:21 ` Lars Povlsen
2020-06-02 19:10 ` Serge Semin
2020-06-09 9:13 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 02/10] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-06-02 19:39 ` Serge Semin
2020-06-09 10:04 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 03/10] spi: dw: Add support for client driver memory operations Lars Povlsen
2020-05-13 14:00 ` [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Lars Povlsen
[not found] ` <20200513145213.GJ4803@sirena.org.uk>
2020-05-19 11:47 ` Lars Povlsen
[not found] ` <20200519115829.GI4611@sirena.org.uk>
2020-05-19 12:10 ` Lars Povlsen
2020-06-02 19:49 ` Serge Semin
2020-06-09 10:27 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Lars Povlsen
[not found] ` <20200513151811.GL4803@sirena.org.uk>
2020-05-19 12:05 ` Lars Povlsen
2020-06-02 21:12 ` Serge Semin
2020-06-10 14:28 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Lars Povlsen
2020-06-02 23:07 ` Serge Semin
2020-06-10 12:27 ` Lars Povlsen
2020-05-13 14:00 ` [PATCH 07/10] " Lars Povlsen
[not found] ` <20200514102516.GD5127@sirena.org.uk>
2020-05-19 9:29 ` Lars Povlsen [this message]
2020-06-02 23:22 ` Serge Semin
2020-05-13 14:00 ` [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Lars Povlsen
2020-05-13 14:00 ` [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-05-13 14:00 ` [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen
2020-05-29 16:21 ` [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Serge Semin
2020-06-02 8:18 ` Lars Povlsen
2020-06-02 8:21 ` Serge Semin
2020-06-02 23:44 ` Serge Semin
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