* [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML
@ 2020-05-20 0:22 Paul Cercueil
2020-05-20 0:22 ` [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt " Paul Cercueil
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml.
In the process, some compatible strings now require a fallback, as the
corresponding SoCs are pin-compatible with their fallback variant.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Use 'pinctrl' instead of 'pin-controller' as the node name
- remove 'additionalProperties: false' since we will have pin conf nodes
.../bindings/pinctrl/ingenic,pinctrl.txt | 81 -----------
.../bindings/pinctrl/ingenic,pinctrl.yaml | 136 ++++++++++++++++++
2 files changed, 136 insertions(+), 81 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
deleted file mode 100644
index d9b2100c98e8..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-Ingenic XBurst pin controller
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
-be used as GPIOs, multiplexed device functions are configured within the
-GPIO port configuration registers and it is typical to refer to pins using the
-naming scheme "PxN" where x is a character identifying the GPIO port with
-which the pin is associated and N is an integer from 0 to 31 identifying the
-pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
-contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
-jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
-
-
-Required properties:
---------------------
-
- - compatible: One of:
- - "ingenic,jz4740-pinctrl"
- - "ingenic,jz4725b-pinctrl"
- - "ingenic,jz4760-pinctrl"
- - "ingenic,jz4760b-pinctrl"
- - "ingenic,jz4770-pinctrl"
- - "ingenic,jz4780-pinctrl"
- - "ingenic,x1000-pinctrl"
- - "ingenic,x1000e-pinctrl"
- - "ingenic,x1500-pinctrl"
- - "ingenic,x1830-pinctrl"
- - reg: Address range of the pinctrl registers.
-
-
-Required properties for sub-nodes (GPIO chips):
------------------------------------------------
-
- - compatible: Must contain one of:
- - "ingenic,jz4740-gpio"
- - "ingenic,jz4760-gpio"
- - "ingenic,jz4770-gpio"
- - "ingenic,jz4780-gpio"
- - "ingenic,x1000-gpio"
- - "ingenic,x1830-gpio"
- - reg: The GPIO bank number.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - interrupts: Interrupt specifier for the controllers interrupt.
- - #interrupt-cells: Should be 2. Refer to
- ../interrupt-controller/interrupts.txt for more details.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
- cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
- GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
- ../gpio/gpio.txt for more details.
-
-
-Example:
---------
-
-pinctrl: pin-controller@10010000 {
- compatible = "ingenic,jz4740-pinctrl";
- reg = <0x10010000 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpa: gpio@0 {
- compatible = "ingenic,jz4740-gpio";
- reg = <0>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&intc>;
- interrupts = <28>;
- };
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
new file mode 100644
index 000000000000..5be2b1e95b36
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs pin controller devicetree bindings
+
+description: >
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
+ may be used as GPIOs, multiplexed device functions are configured within the
+ GPIO port configuration registers and it is typical to refer to pins using the
+ naming scheme "PxN" where x is a character identifying the GPIO port with
+ which the pin is associated and N is an integer from 0 to 31 identifying the
+ pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
+ and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
+ contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
+ JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
+ pins.
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ nodename:
+ pattern: "^pinctrl@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-pinctrl
+ - ingenic,jz4725b-pinctrl
+ - ingenic,jz4760-pinctrl
+ - ingenic,jz4770-pinctrl
+ - ingenic,jz4780-pinctrl
+ - ingenic,x1000-pinctrl
+ - ingenic,x1500-pinctrl
+ - ingenic,x1830-pinctrl
+ - items:
+ - const: ingenic,jz4760b-pinctrl
+ - const: ingenic,jz4760-pinctrl
+ - items:
+ - const: ingenic,x1000e-pinctrl
+ - const: ingenic,x1000-pinctrl
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^gpio@[0-9]$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-gpio
+ - ingenic,jz4725b-gpio
+ - ingenic,jz4760-gpio
+ - ingenic,jz4770-gpio
+ - ingenic,jz4780-gpio
+ - ingenic,x1000-gpio
+ - ingenic,x1500-gpio
+ - ingenic,x1830-gpio
+
+ reg:
+ items:
+ - description: The GPIO bank number
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+ description:
+ Refer to ../interrupt-controller/interrupts.txt for more details.
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ pin-controller@10010000 {
+ compatible = "ingenic,jz4770-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@0 {
+ compatible = "ingenic,jz4770-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+ };
--
2.26.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt to YAML
2020-05-20 0:22 [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML Paul Cercueil
@ 2020-05-20 0:22 ` Paul Cercueil
2020-05-28 21:45 ` Rob Herring
2020-05-20 0:22 ` [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt " Paul Cercueil
2020-05-28 21:42 ` [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt " Rob Herring
2 siblings, 1 reply; 7+ messages in thread
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
Convert the ingenic,jz4780-nemc.txt doc file to ingenic,nemc.yaml.
The ingenic,jz4725b-nemc compatible string was added in the process,
with a fallback to ingenic,jz4740-nemc.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Inline content of ingenic,nemc-client.yaml inside ingenic,nemc.yaml
- Add missing 'reg' property to sub-nodes and mark it as required
- Use a more generic wildcard to match all sub-nodes.
.../ingenic,jz4780-nemc.txt | 76 -----------
.../memory-controllers/ingenic,nemc.yaml | 126 ++++++++++++++++++
2 files changed, 126 insertions(+), 76 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt b/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
deleted file mode 100644
index 59b8dcc118ee..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
+++ /dev/null
@@ -1,76 +0,0 @@
-* Ingenic JZ4780 NAND/external memory controller (NEMC)
-
-This file documents the device tree bindings for the NEMC external memory
-controller in Ingenic JZ4780
-
-Required properties:
-- compatible: Should be set to one of:
- "ingenic,jz4740-nemc" (JZ4740)
- "ingenic,jz4780-nemc" (JZ4780)
-- reg: Should specify the NEMC controller registers location and length.
-- clocks: Clock for the NEMC controller.
-- #address-cells: Must be set to 2.
-- #size-cells: Must be set to 1.
-- ranges: A set of ranges for each bank describing the physical memory layout.
- Each should specify the following 4 integer values:
-
- <cs number> 0 <physical address of mapping> <size of mapping>
-
-Each child of the NEMC node describes a device connected to the NEMC.
-
-Required child node properties:
-- reg: Should contain at least one register specifier, given in the following
- format:
-
- <cs number> <offset> <size>
-
- Multiple registers can be specified across multiple banks. This is needed,
- for example, for packaged NAND devices with multiple dies. Such devices
- should be grouped into a single node.
-
-Optional child node properties:
-- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits.
-- ingenic,nemc-tAS: Address setup time in nanoseconds.
-- ingenic,nemc-tAH: Address hold time in nanoseconds.
-- ingenic,nemc-tBP: Burst pitch time in nanoseconds.
-- ingenic,nemc-tAW: Access wait time in nanoseconds.
-- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds.
-
-If a child node references multiple banks in its "reg" property, the same value
-for all optional parameters will be configured for all banks. If any optional
-parameters are omitted, they will be left unchanged from whatever they are
-configured to when the NEMC device is probed (which may be the reset value as
-given in the hardware reference manual, or a value configured by the boot
-loader).
-
-Example (NEMC node with a NAND child device attached at CS1):
-
-nemc: nemc@13410000 {
- compatible = "ingenic,jz4780-nemc";
- reg = <0x13410000 0x10000>;
-
- #address-cells = <2>;
- #size-cells = <1>;
-
- ranges = <1 0 0x1b000000 0x1000000
- 2 0 0x1a000000 0x1000000
- 3 0 0x19000000 0x1000000
- 4 0 0x18000000 0x1000000
- 5 0 0x17000000 0x1000000
- 6 0 0x16000000 0x1000000>;
-
- clocks = <&cgu JZ4780_CLK_NEMC>;
-
- nand: nand@1 {
- compatible = "ingenic,jz4780-nand";
- reg = <1 0 0x1000000>;
-
- ingenic,nemc-tAS = <10>;
- ingenic,nemc-tAH = <5>;
- ingenic,nemc-tBP = <10>;
- ingenic,nemc-tAW = <15>;
- ingenic,nemc-tSTRV = <100>;
-
- ...
- };
-};
diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
new file mode 100644
index 000000000000..9b478da0c479
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ $nodename:
+ pattern: "^memory-controller@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-nemc
+ - ingenic,jz4780-nemc
+ - items:
+ - const: ingenic,jz4725b-nemc
+ - const: ingenic,jz4740-nemc
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+patternProperties:
+ ".*@[0-9]+$":
+ type: object
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 255
+
+ ingenic,nemc-bus-width:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [8, 16]
+ description: Specifies the bus width in bits.
+
+ ingenic,nemc-tAS:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address setup time in nanoseconds.
+
+ ingenic,nemc-tAH:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address hold time in nanoseconds.
+
+ ingenic,nemc-tBP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Burst pitch time in nanoseconds.
+
+ ingenic,nemc-tAW:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address wait time in nanoseconds.
+
+ ingenic,nemc-tSTRV:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Static memory recovery time in nanoseconds.
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ #include <dt-bindings/gpio/gpio.h>
+ nemc: memory-controller@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000>,
+ <2 0 0x1a000000 0x1000000>,
+ <3 0 0x19000000 0x1000000>,
+ <4 0 0x18000000 0x1000000>,
+ <5 0 0x17000000 0x1000000>,
+ <6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ ethernet@6 {
+ compatible = "davicom,dm9000";
+ davicom,no-eeprom;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs6>;
+
+ reg = <6 0 1>, /* addr */
+ <6 2 1>; /* data */
+
+ ingenic,nemc-tAS = <15>;
+ ingenic,nemc-tAH = <10>;
+ ingenic,nemc-tBP = <20>;
+ ingenic,nemc-tAW = <50>;
+ ingenic,nemc-tSTRV = <100>;
+
+ reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <ð0_power>;
+
+ interrupt-parent = <&gpe>;
+ interrupts = <19 4>;
+ };
+ };
--
2.26.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt to YAML
2020-05-20 0:22 ` [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt " Paul Cercueil
@ 2020-05-28 21:45 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2020-05-28 21:45 UTC (permalink / raw)
To: Paul Cercueil
Cc: od, linux-gpio, devicetree, linux-kernel, Boris Brezillon,
Rob Herring, linux-mtd
On Wed, 20 May 2020 02:22:33 +0200, Paul Cercueil wrote:
> Convert the ingenic,jz4780-nemc.txt doc file to ingenic,nemc.yaml.
>
> The ingenic,jz4725b-nemc compatible string was added in the process,
> with a fallback to ingenic,jz4740-nemc.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>
> Notes:
> v2: - Inline content of ingenic,nemc-client.yaml inside ingenic,nemc.yaml
> - Add missing 'reg' property to sub-nodes and mark it as required
> - Use a more generic wildcard to match all sub-nodes.
>
> .../ingenic,jz4780-nemc.txt | 76 -----------
> .../memory-controllers/ingenic,nemc.yaml | 126 ++++++++++++++++++
> 2 files changed, 126 insertions(+), 76 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt to YAML
2020-05-20 0:22 [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML Paul Cercueil
2020-05-20 0:22 ` [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt " Paul Cercueil
@ 2020-05-20 0:22 ` Paul Cercueil
2020-05-28 21:45 ` Rob Herring
2020-05-28 21:42 ` [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt " Rob Herring
2 siblings, 1 reply; 7+ messages in thread
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
Convert the ingenic,jz4780-nand.txt doc file to ingenic,nand.yaml.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Don't include ingenic,nemc-client.yaml which is gone
- Use 'partitions' property instead of '^partitions$' pattern
.../bindings/mtd/ingenic,jz4780-nand.txt | 92 ------------
.../devicetree/bindings/mtd/ingenic,nand.yaml | 132 ++++++++++++++++++
2 files changed, 132 insertions(+), 92 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
deleted file mode 100644
index c02259353327..000000000000
--- a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-* Ingenic JZ4780 NAND/ECC
-
-This file documents the device tree bindings for NAND flash devices on the
-JZ4780. NAND devices are connected to the NEMC controller (described in
-memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
-be children of the NEMC node.
-
-Required NAND controller device properties:
-- compatible: Should be one of:
- * ingenic,jz4740-nand
- * ingenic,jz4725b-nand
- * ingenic,jz4780-nand
-- reg: For each bank with a NAND chip attached, should specify a bank number,
- an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
-
-Optional NAND controller device properties:
-- ecc-engine: To make use of the hardware ECC controller, this
- property must contain a phandle for the ECC controller node. The required
- properties for this node are described below. If this is not specified,
- software ECC will be used instead.
-
-Optional children nodes:
-- Individual NAND chips are children of the NAND controller node.
-
-Required children node properties:
-- reg: An integer ranging from 1 to 6 representing the CS line to use.
-
-Optional children node properties:
-- nand-ecc-step-size: ECC block size in bytes.
-- nand-ecc-strength: ECC strength (max number of correctable bits).
-- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
-- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
-- rb-gpios: GPIO specifier for the busy pin.
-- wp-gpios: GPIO specifier for the write protect pin.
-
-Optional child node of NAND chip nodes:
-- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
-
-nemc: nemc@13410000 {
- ...
-
- nandc: nand-controller@1 {
- compatible = "ingenic,jz4780-nand";
- reg = <1 0 0x1000000>; /* Bank 1 */
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- ecc-engine = <&bch>;
-
- nand@1 {
- reg = <1>;
-
- nand-ecc-step-size = <1024>;
- nand-ecc-strength = <24>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
-
- rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
-
- partitions {
- #address-cells = <2>;
- #size-cells = <2>;
- ...
- }
- };
- };
-};
-
-The ECC controller is a separate SoC component used for error correction on
-NAND devices. The following is a description of the device properties for a
-ECC controller.
-
-Required ECC properties:
-- compatible: Should be one of:
- * ingenic,jz4740-ecc
- * ingenic,jz4725b-bch
- * ingenic,jz4780-bch
-- reg: Should specify the ECC controller registers location and length.
-- clocks: Clock for the ECC controller.
-
-Example:
-
-bch: bch@134d0000 {
- compatible = "ingenic,jz4780-bch";
- reg = <0x134d0000 0x10000>;
-
- clocks = <&cgu JZ4780_CLK_BCH>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml b/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
new file mode 100644
index 000000000000..8abb6d463cb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs NAND controller devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-nand
+ - ingenic,jz4725b-nand
+ - ingenic,jz4780-nand
+
+ reg:
+ items:
+ - description: Bank number, offset and size of first attached NAND chip
+ - description: Bank number, offset and size of second attached NAND chip
+ - description: Bank number, offset and size of third attached NAND chip
+ - description: Bank number, offset and size of fourth attached NAND chip
+ minItems: 1
+
+ ecc-engine: true
+
+ partitions:
+ type: object
+ description:
+ Node containing description of fixed partitions.
+ See Documentation/devicetree/bindings/mtd/partition.txt
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ rb-gpios:
+ description: GPIO specifier for the busy pin.
+ maxItems: 1
+
+ wp-gpios:
+ description: GPIO specifier for the write-protect pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ memory-controller@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000>,
+ <2 0 0x1a000000 0x1000000>,
+ <3 0 0x19000000 0x1000000>,
+ <4 0 0x18000000 0x1000000>,
+ <5 0 0x17000000 0x1000000>,
+ <6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x1000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ecc-engine = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x800000>;
+ };
+
+ partition@800000 {
+ label = "u-boot";
+ reg = <0x0 0x800000 0x0 0x200000>;
+ };
+
+ partition@a00000 {
+ label = "u-boot-env";
+ reg = <0x0 0xa00000 0x0 0x200000>;
+ };
+
+ partition@c00000 {
+ label = "boot";
+ reg = <0x0 0xc00000 0x0 0x4000000>;
+ };
+
+ partition@4c00000 {
+ label = "system";
+ reg = <0x0 0x4c00000 0x1 0xfb400000>;
+ };
+ };
+ };
+ };
+ };
--
2.26.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt to YAML
2020-05-20 0:22 ` [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt " Paul Cercueil
@ 2020-05-28 21:45 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2020-05-28 21:45 UTC (permalink / raw)
To: Paul Cercueil
Cc: Boris Brezillon, od, Rob Herring, devicetree, linux-mtd,
linux-kernel, linux-gpio
On Wed, 20 May 2020 02:22:34 +0200, Paul Cercueil wrote:
> Convert the ingenic,jz4780-nand.txt doc file to ingenic,nand.yaml.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>
> Notes:
> v2: - Don't include ingenic,nemc-client.yaml which is gone
> - Use 'partitions' property instead of '^partitions$' pattern
>
> .../bindings/mtd/ingenic,jz4780-nand.txt | 92 ------------
> .../devicetree/bindings/mtd/ingenic,nand.yaml | 132 ++++++++++++++++++
> 2 files changed, 132 insertions(+), 92 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML
2020-05-20 0:22 [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML Paul Cercueil
2020-05-20 0:22 ` [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt " Paul Cercueil
2020-05-20 0:22 ` [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt " Paul Cercueil
@ 2020-05-28 21:42 ` Rob Herring
2020-05-30 11:04 ` Paul Cercueil
2 siblings, 1 reply; 7+ messages in thread
From: Rob Herring @ 2020-05-28 21:42 UTC (permalink / raw)
To: Paul Cercueil
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd, linux-gpio
On Wed, May 20, 2020 at 02:22:32AM +0200, Paul Cercueil wrote:
> Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml.
>
> In the process, some compatible strings now require a fallback, as the
> corresponding SoCs are pin-compatible with their fallback variant.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>
> Notes:
> v2: - Use 'pinctrl' instead of 'pin-controller' as the node name
> - remove 'additionalProperties: false' since we will have pin conf nodes
You need to describe those nodes and not just allow anything.
>
> .../bindings/pinctrl/ingenic,pinctrl.txt | 81 -----------
> .../bindings/pinctrl/ingenic,pinctrl.yaml | 136 ++++++++++++++++++
> 2 files changed, 136 insertions(+), 81 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
> diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
> new file mode 100644
> index 000000000000..5be2b1e95b36
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ingenic SoCs pin controller devicetree bindings
> +
> +description: >
> + Please refer to pinctrl-bindings.txt in this directory for details of the
> + common pinctrl bindings used by client devices, including the meaning of the
> + phrase "pin configuration node".
> +
> + For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
> + may be used as GPIOs, multiplexed device functions are configured within the
> + GPIO port configuration registers and it is typical to refer to pins using the
> + naming scheme "PxN" where x is a character identifying the GPIO port with
> + which the pin is associated and N is an integer from 0 to 31 identifying the
> + pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
> + and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
> + contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
> + JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
> + pins.
> +
> +maintainers:
> + - Paul Cercueil <paul@crapouillou.net>
> +
> +properties:
> + nodename:
It's $nodename as that's not a real property. And that will expose the
error in the example for you.
> + pattern: "^pinctrl@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - enum:
> + - ingenic,jz4740-pinctrl
> + - ingenic,jz4725b-pinctrl
> + - ingenic,jz4760-pinctrl
> + - ingenic,jz4770-pinctrl
> + - ingenic,jz4780-pinctrl
> + - ingenic,x1000-pinctrl
> + - ingenic,x1500-pinctrl
> + - ingenic,x1830-pinctrl
> + - items:
> + - const: ingenic,jz4760b-pinctrl
> + - const: ingenic,jz4760-pinctrl
> + - items:
> + - const: ingenic,x1000e-pinctrl
> + - const: ingenic,x1000-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^gpio@[0-9]$":
> + type: object
> + properties:
> + compatible:
> + enum:
> + - ingenic,jz4740-gpio
> + - ingenic,jz4725b-gpio
> + - ingenic,jz4760-gpio
> + - ingenic,jz4770-gpio
> + - ingenic,jz4780-gpio
> + - ingenic,x1000-gpio
> + - ingenic,x1500-gpio
> + - ingenic,x1830-gpio
> +
> + reg:
> + items:
> + - description: The GPIO bank number
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> + description:
> + Refer to ../interrupt-controller/interrupts.txt for more details.
> +
> + interrupts:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - gpio-controller
> + - "#gpio-cells"
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> +
> +examples:
> + - |
> + pin-controller@10010000 {
> + compatible = "ingenic,jz4770-pinctrl";
> + reg = <0x10010000 0x600>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio@0 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <0>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <17>;
> + };
> + };
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML
2020-05-28 21:42 ` [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt " Rob Herring
@ 2020-05-30 11:04 ` Paul Cercueil
0 siblings, 0 replies; 7+ messages in thread
From: Paul Cercueil @ 2020-05-30 11:04 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd, linux-gpio
Hi Rob,
Le jeu. 28 mai 2020 à 15:42, Rob Herring <robh@kernel.org> a écrit :
> On Wed, May 20, 2020 at 02:22:32AM +0200, Paul Cercueil wrote:
>> Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml.
>>
>> In the process, some compatible strings now require a fallback, as
>> the
>> corresponding SoCs are pin-compatible with their fallback variant.
>>
>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>>
>> Notes:
>> v2: - Use 'pinctrl' instead of 'pin-controller' as the node name
>> - remove 'additionalProperties: false' since we will have
>> pin conf nodes
>
> You need to describe those nodes and not just allow anything.
These nodes don't have any constraint on their name, so I would need a
wildcard property for children nodes. That's not something I can
express in YAML right now, is it?
-Paul
>>
>> .../bindings/pinctrl/ingenic,pinctrl.txt | 81 -----------
>> .../bindings/pinctrl/ingenic,pinctrl.yaml | 136
>> ++++++++++++++++++
>> 2 files changed, 136 insertions(+), 81 deletions(-)
>> delete mode 100644
>> Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
>> create mode 100644
>> Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
>
>
>> diff --git
>> a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
>> b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
>> new file mode 100644
>> index 000000000000..5be2b1e95b36
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
>> @@ -0,0 +1,136 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Ingenic SoCs pin controller devicetree bindings
>> +
>> +description: >
>> + Please refer to pinctrl-bindings.txt in this directory for
>> details of the
>> + common pinctrl bindings used by client devices, including the
>> meaning of the
>> + phrase "pin configuration node".
>> +
>> + For the Ingenic SoCs, pin control is tightly bound with GPIO
>> ports. All pins
>> + may be used as GPIOs, multiplexed device functions are
>> configured within the
>> + GPIO port configuration registers and it is typical to refer to
>> pins using the
>> + naming scheme "PxN" where x is a character identifying the GPIO
>> port with
>> + which the pin is associated and N is an integer from 0 to 31
>> identifying the
>> + pin within that GPIO port. For example PA0 is the first pin in
>> GPIO port A,
>> + and PB31 is the last pin in GPIO port B. The JZ4740, the X1000
>> and the X1830
>> + contains 4 GPIO ports, PA to PD, for a total of 128 pins. The
>> JZ4760, the
>> + JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a
>> total of 192
>> + pins.
>> +
>> +maintainers:
>> + - Paul Cercueil <paul@crapouillou.net>
>> +
>> +properties:
>> + nodename:
>
> It's $nodename as that's not a real property. And that will expose the
> error in the example for you.
>
>> + pattern: "^pinctrl@[0-9a-f]+$"
>> +
>> + compatible:
>> + oneOf:
>> + - enum:
>> + - ingenic,jz4740-pinctrl
>> + - ingenic,jz4725b-pinctrl
>> + - ingenic,jz4760-pinctrl
>> + - ingenic,jz4770-pinctrl
>> + - ingenic,jz4780-pinctrl
>> + - ingenic,x1000-pinctrl
>> + - ingenic,x1500-pinctrl
>> + - ingenic,x1830-pinctrl
>> + - items:
>> + - const: ingenic,jz4760b-pinctrl
>> + - const: ingenic,jz4760-pinctrl
>> + - items:
>> + - const: ingenic,x1000e-pinctrl
>> + - const: ingenic,x1000-pinctrl
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 0
>> +
>> +patternProperties:
>> + "^gpio@[0-9]$":
>> + type: object
>> + properties:
>> + compatible:
>> + enum:
>> + - ingenic,jz4740-gpio
>> + - ingenic,jz4725b-gpio
>> + - ingenic,jz4760-gpio
>> + - ingenic,jz4770-gpio
>> + - ingenic,jz4780-gpio
>> + - ingenic,x1000-gpio
>> + - ingenic,x1500-gpio
>> + - ingenic,x1830-gpio
>> +
>> + reg:
>> + items:
>> + - description: The GPIO bank number
>> +
>> + gpio-controller: true
>> +
>> + "#gpio-cells":
>> + const: 2
>> +
>> + gpio-ranges:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + "#interrupt-cells":
>> + const: 2
>> + description:
>> + Refer to ../interrupt-controller/interrupts.txt for more
>> details.
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + required:
>> + - compatible
>> + - reg
>> + - gpio-controller
>> + - "#gpio-cells"
>> + - interrupts
>> + - interrupt-controller
>> + - "#interrupt-cells"
>> +
>> + additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - "#address-cells"
>> + - "#size-cells"
>> +
>> +examples:
>> + - |
>> + pin-controller@10010000 {
>> + compatible = "ingenic,jz4770-pinctrl";
>> + reg = <0x10010000 0x600>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + gpio@0 {
>> + compatible = "ingenic,jz4770-gpio";
>> + reg = <0>;
>> +
>> + gpio-controller;
>> + gpio-ranges = <&pinctrl 0 0 32>;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <17>;
>> + };
>> + };
>> --
>> 2.26.2
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-30 11:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-20 0:22 [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML Paul Cercueil
2020-05-20 0:22 ` [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt " Paul Cercueil
2020-05-28 21:45 ` Rob Herring
2020-05-20 0:22 ` [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt " Paul Cercueil
2020-05-28 21:45 ` Rob Herring
2020-05-28 21:42 ` [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt " Rob Herring
2020-05-30 11:04 ` Paul Cercueil
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