* [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates
@ 2020-07-09 22:30 Florian Fainelli
2020-07-09 22:30 ` [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source Florian Fainelli
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
Hi Marc,
This patch series contains a number of updates for Broadcom STB L2
interrupt controllers to enable them as wake-up interrupt controllers,
and add missing compatible strings that should be matched.
Thanks!
Florian Fainelli (3):
dt-bindings: interrupt-controller: Document Broadcom STB HIF L2
dt-bindings: interrupt-controller: Document UPG auxiliary L2
irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
Justin Chen (2):
irqchip/bcm7120-l2: Set controller as wake-up source
irqchip/brcmstb-l2: Set controller as wake-up source
Kamal Dasu (1):
irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible
.../bindings/interrupt-controller/brcm,l2-intc.txt | 5 ++++-
drivers/irqchip/irq-bcm7120-l2.c | 8 +++++---
drivers/irqchip/irq-brcmstb-l2.c | 5 +++++
3 files changed, 14 insertions(+), 4 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-09 22:30 ` [PATCH 2/6] irqchip/brcmstb-l2: " Florian Fainelli
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Justin Chen, Florian Fainelli, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Rob Herring,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
From: Justin Chen <justinpopo6@gmail.com>
Utilize the Broadcom interrupt controller standard property
"brcm,irq-can-wake" to flag whether this particular interrupt controller
instance is wake-up capable.
Since we do not know what type of parent interrupt controller we are
interfaced with, ensure that enable_irq_wake() is called early on.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/irqchip/irq-bcm7120-l2.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index 586df3587be0..c7c9e976acbb 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -143,6 +143,9 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn,
irq_set_chained_handler_and_data(parent_irq,
bcm7120_l2_intc_irq_handle, l1_data);
+ if (data->can_wake)
+ enable_irq_wake(parent_irq);
+
return 0;
}
@@ -247,6 +250,8 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn,
if (ret < 0)
goto out_free_l1_data;
+ data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
+
for (irq = 0; irq < data->num_parent_irqs; irq++) {
ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
if (ret)
@@ -274,9 +279,6 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn,
goto out_free_domain;
}
- if (of_property_read_bool(dn, "brcm,irq-can-wake"))
- data->can_wake = true;
-
for (idx = 0; idx < data->n_words; idx++) {
irq = idx * IRQS_PER_WORD;
gc = irq_get_domain_generic_chip(data->domain, irq);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/6] irqchip/brcmstb-l2: Set controller as wake-up source
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
2020-07-09 22:30 ` [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-09 22:30 ` [PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2 Florian Fainelli
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Justin Chen, Florian Fainelli, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Rob Herring,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
From: Justin Chen <justinpopo6@gmail.com>
Utilize the Broadcom interrupt controller standard property
"brcm,irq-can-wake" to flag whether this particular interrupt controller
instance is wake-up capable.
Since we do not know what type of parent interrupt controller we are
interfaced with, ensure that enable_irq_wake() is called early on.
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/irqchip/irq-brcmstb-l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 0298ede67e51..157fad184bdc 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -254,6 +254,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
*/
data->gc->wake_enabled = 0xffffffff;
ct->chip.irq_set_wake = irq_gc_set_wake;
+ enable_irq_wake(parent_irq);
}
pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
2020-07-09 22:30 ` [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source Florian Fainelli
2020-07-09 22:30 ` [PATCH 2/6] irqchip/brcmstb-l2: " Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-09 22:30 ` [PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible Florian Fainelli
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
Add documentation for the brcm,hif-spi-l2-intc compatible string to the
brcm,l2-intc.txt binding document.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/interrupt-controller/brcm,l2-intc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
index d514ec060a4a..98602f1d1e91 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
@@ -2,7 +2,9 @@ Broadcom Generic Level 2 Interrupt Controller
Required properties:
-- compatible: should be "brcm,l2-intc" for latched interrupt controllers
+- compatible: should be one of:
+ "brcm,hif-spi-l2-intc" or
+ "brcm,l2-intc" for latched interrupt controllers
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
` (2 preceding siblings ...)
2020-07-09 22:30 ` [PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2 Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-09 22:30 ` [PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2 Florian Fainelli
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Kamal Dasu, Florian Fainelli, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Rob Herring,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
From: Kamal Dasu <kdasu.kdev@gmail.com>
The HIF_SPI_INTR2 Level 2 interrupt controller node is defined with the
"brcm,hif-spi-l2-intc" compatible string in Device Tree and behaves as
an edge triggered standard Broadcom STB L2 interrupt controller.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/irqchip/irq-brcmstb-l2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 157fad184bdc..b10fe5042a2f 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -276,6 +276,8 @@ static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
}
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
+IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
+ brcmstb_l2_edge_intc_of_init);
static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
struct device_node *parent)
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
` (3 preceding siblings ...)
2020-07-09 22:30 ` [PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-09 22:30 ` [PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible Florian Fainelli
2020-07-17 12:48 ` [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Marc Zyngier
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
Define the compatible string brcm,upg-aux-aon-l2-intc which is used by
the Broadcom STB UPG auxiliary always-on interrupt controller.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/interrupt-controller/brcm,l2-intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
index 98602f1d1e91..021cf822395c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: should be one of:
"brcm,hif-spi-l2-intc" or
+ "brcm,upg-aux-aon-l2-intc" or
"brcm,l2-intc" for latched interrupt controllers
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
- reg: specifies the base physical address and size of the registers
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
` (4 preceding siblings ...)
2020-07-09 22:30 ` [PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2 Florian Fainelli
@ 2020-07-09 22:30 ` Florian Fainelli
2020-07-17 12:48 ` [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Marc Zyngier
6 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2020-07-09 22:30 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Thomas Gleixner, Jason Cooper, Marc Zyngier,
Rob Herring, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE
The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with
the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and
behaves as an edge triggered standard Broadcom STB L2 interrupt
controller.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/irqchip/irq-brcmstb-l2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index b10fe5042a2f..cdd6a42d4efa 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -278,6 +278,8 @@ static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
brcmstb_l2_edge_intc_of_init);
+IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
+ brcmstb_l2_edge_intc_of_init);
static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
struct device_node *parent)
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
` (5 preceding siblings ...)
2020-07-09 22:30 ` [PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible Florian Fainelli
@ 2020-07-17 12:48 ` Marc Zyngier
6 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2020-07-17 12:48 UTC (permalink / raw)
To: Alexandre Torgue, Jason Cooper, Thomas Gleixner, linux-kernel,
Florian Fainelli
Cc: marex, linux-arm-kernel, linux-gpio, linux-stm32,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:BROADCOM BMIPS MIPS ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring
On Thu, 9 Jul 2020 15:30:10 -0700, Florian Fainelli wrote:
> This patch series contains a number of updates for Broadcom STB L2
> interrupt controllers to enable them as wake-up interrupt controllers,
> and add missing compatible strings that should be matched.
>
> Thanks!
>
> Florian Fainelli (3):
> dt-bindings: interrupt-controller: Document Broadcom STB HIF L2
> dt-bindings: interrupt-controller: Document UPG auxiliary L2
> irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
>
> [...]
Applied to irq/irqchip-5.9, thanks!
[1/6] irqchip/bcm7120-l2: Set controller as wake-up source
commit: f4ccb74569aaf839c2830382e902dd50d564df55
[2/6] irqchip/brcmstb-l2: Set controller as wake-up source
commit: c8d8d6fc478a30f3e8ea5372664dd2a808c4311e
[3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2
commit: 90b06e2dc4d1e8e9311a5275d53f61d90b61efdc
[4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible
commit: 9ac793dc5c97691152818305974299604c67e110
[5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2
commit: 03a7ac47c14c7ef50742a34b3cfba1a47a578a03
[6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
commit: 240e176a96187ee84e63626ca0d1aac92da503aa
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-07-17 12:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
2020-07-09 22:30 ` [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source Florian Fainelli
2020-07-09 22:30 ` [PATCH 2/6] irqchip/brcmstb-l2: " Florian Fainelli
2020-07-09 22:30 ` [PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2 Florian Fainelli
2020-07-09 22:30 ` [PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible Florian Fainelli
2020-07-09 22:30 ` [PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2 Florian Fainelli
2020-07-09 22:30 ` [PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible Florian Fainelli
2020-07-17 12:48 ` [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Marc Zyngier
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).