* [PATCH v4 1/5] arm64: Add config for Keem Bay SoC
2020-07-17 9:04 [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
@ 2020-07-17 9:04 ` Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Daniele Alessandrelli @ 2020-07-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel, SoC Team, Rob Herring, Arnd Bergmann, Olof Johansson
Cc: Daniele Alessandrelli, devicetree, linux-kernel, Jassi Brar,
Catalin Marinas, Will Deacon, Paul J. Murphy, Paul J. Murphy,
Dinh Nguyen
From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
arch/arm64/Kconfig.platforms | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 8dd05b2a925c..95c1b9042009 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -121,6 +121,11 @@ config ARCH_HISI
help
This enables support for Hisilicon ARMv8 SoC family
+config ARCH_KEEMBAY
+ bool "Keem Bay SoC"
+ help
+ This enables support for Intel Movidius SoC code-named Keem Bay.
+
config ARCH_MEDIATEK
bool "MediaTek SoC Family"
select ARM_GIC
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 2/5] dt-bindings: arm: Add Keem Bay bindings
2020-07-17 9:04 [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
@ 2020-07-17 9:04 ` Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC Daniele Alessandrelli
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Daniele Alessandrelli @ 2020-07-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel, SoC Team, Rob Herring, Arnd Bergmann, Olof Johansson
Cc: Daniele Alessandrelli, devicetree, linux-kernel, Jassi Brar,
Catalin Marinas, Will Deacon, Paul J. Murphy, Paul J. Murphy,
Dinh Nguyen
From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
.../bindings/arm/intel,keembay.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/intel,keembay.yaml
diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml
new file mode 100644
index 000000000000..4d925785f504
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Keem Bay platform device tree bindings
+
+maintainers:
+ - Paul J. Murphy <paul.j.murphy@intel.com>
+ - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - intel,keembay-evm
+ - const: intel,keembay
+...
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC
2020-07-17 9:04 [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
@ 2020-07-17 9:04 ` Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 4/5] arm64: dts: keembay: Add device tree " Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board Daniele Alessandrelli
4 siblings, 0 replies; 6+ messages in thread
From: Daniele Alessandrelli @ 2020-07-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel, SoC Team, Rob Herring, Arnd Bergmann, Olof Johansson
Cc: Daniele Alessandrelli, devicetree, linux-kernel, Jassi Brar,
Catalin Marinas, Will Deacon, Paul J. Murphy, Paul J. Murphy,
Dinh Nguyen
From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Add maintainers for the new Intel Movidius SoC code-named Keem Bay.
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b4a43a9e7fbc..3babb333b556 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1954,6 +1954,12 @@ F: drivers/irqchip/irq-ixp4xx.c
F: include/linux/irqchip/irq-ixp4xx.h
F: include/linux/platform_data/timer-ixp4xx.h
+ARM/INTEL KEEMBAY ARCHITECTURE
+M: Paul J. Murphy <paul.j.murphy@intel.com>
+M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+S: Maintained
+F: Documentation/devicetree/bindings/arm/intel,keembay.yaml
+
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron <jic23@cam.ac.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 4/5] arm64: dts: keembay: Add device tree for Keem Bay SoC
2020-07-17 9:04 [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
` (2 preceding siblings ...)
2020-07-17 9:04 ` [PATCH v4 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC Daniele Alessandrelli
@ 2020-07-17 9:04 ` Daniele Alessandrelli
2020-07-17 9:04 ` [PATCH v4 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board Daniele Alessandrelli
4 siblings, 0 replies; 6+ messages in thread
From: Daniele Alessandrelli @ 2020-07-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel, SoC Team, Rob Herring, Arnd Bergmann, Olof Johansson
Cc: Daniele Alessandrelli, devicetree, linux-kernel, Jassi Brar,
Catalin Marinas, Will Deacon, Paul J. Murphy, Paul J. Murphy,
Dinh Nguyen
From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Add initial device tree for Intel Movidius SoC code-named Keem Bay.
This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 +++++++++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 3babb333b556..82ca9748fb70 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M: Paul J. Murphy <paul.j.murphy@intel.com>
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
S: Maintained
F: Documentation/devicetree/bindings/arm/intel,keembay.yaml
+F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron <jic23@cam.ac.uk>
diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
new file mode 100644
index 000000000000..781761d2942b
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020, Intel Corporation.
+ *
+ * Device tree describing Keem Bay SoC.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ gic: interrupt-controller@20500000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
+ <0x0 0x20580000 0x0 0x80000>; /* GICR */
+ /* VGIC maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Secure, non-secure, virtual, and hypervisor */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart0: serial@20150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20150000 0x0 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@20160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20160000 0x0 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@20170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20170000 0x0 0x100>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@20180000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20180000 0x0 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+ };
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board
2020-07-17 9:04 [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
` (3 preceding siblings ...)
2020-07-17 9:04 ` [PATCH v4 4/5] arm64: dts: keembay: Add device tree " Daniele Alessandrelli
@ 2020-07-17 9:04 ` Daniele Alessandrelli
4 siblings, 0 replies; 6+ messages in thread
From: Daniele Alessandrelli @ 2020-07-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel, SoC Team, Rob Herring, Arnd Bergmann, Olof Johansson
Cc: Daniele Alessandrelli, devicetree, linux-kernel, Jassi Brar,
Catalin Marinas, Will Deacon, Paul J. Murphy, Paul J. Murphy,
Dinh Nguyen
From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/intel/Makefile | 1 +
arch/arm64/boot/dts/intel/keembay-evm.dts | 37 +++++++++++++++++++++++
3 files changed, 39 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 82ca9748fb70..aa86a74ea5d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M: Paul J. Murphy <paul.j.murphy@intel.com>
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
S: Maintained
F: Documentation/devicetree/bindings/arm/intel,keembay.yaml
+F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 40cb16e8c814..296eceec4276 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb
+dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts
new file mode 100644
index 000000000000..466c85363a29
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-evm.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020, Intel Corporation
+ *
+ * Device tree describing Keem Bay EVM board.
+ */
+
+/dts-v1/;
+
+#include "keembay-soc.dtsi"
+
+/ {
+ model = "Keem Bay EVM";
+ compatible = "intel,keembay-evm", "intel,keembay";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2GB of DDR memory. */
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+};
+
+&uart3 {
+ status = "okay";
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread