* [PATCH 0/9] msm8992/4 updates @ 2020-07-28 12:00 Konrad Dybcio 2020-07-28 12:00 ` [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 Konrad Dybcio ` (8 more replies) 0 siblings, 9 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This series brings support for: * sdhci2 on 8992/4 * BLSP_I2C1 (a seemingly WP-exclusive i2c bus) for 8992 * Synaptics RMI4 touchscreen for Sony Kitakami and MSFT L950 * DWC3 USB for msm8992/4 (doesn't work on Lumias, they use custom circuitry) * Missing clocks for 8994 GCC needed for USB Konrad Dybcio (9): arm64: dts: qcom: msm8992: Add support for SDHCI2 arm64: dts: qcom: msm8992: Add BLSP_I2C1 support arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen arm64: dts: qcom: msm8994: Add USB support arm64: dts: qcom: msm8992: Add USB support clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs arm64: dts: qcom: kitakami: Add Synaptics touchscreen arm64: dts: qcom: msm8994: Add SDHCI2 node arm64: dts: qcom: kitakami: Enable SDHCI2 .../dts/qcom/msm8992-msft-lumia-talkman.dts | 28 ++ arch/arm64/boot/dts/qcom/msm8992.dtsi | 124 ++++++ .../qcom/msm8994-sony-xperia-kitakami.dtsi | 49 ++- arch/arm64/boot/dts/qcom/msm8994.dtsi | 89 ++++ drivers/clk/qcom/gcc-msm8994.c | 388 +++++++++++++++++- include/dt-bindings/clock/qcom,gcc-msm8994.h | 36 ++ 6 files changed, 712 insertions(+), 2 deletions(-) -- 2.27.0 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 2/9] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support Konrad Dybcio ` (7 subsequent siblings) 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This will let us use SD cards on our devices. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 188fff2095f1..9b42ac42b171 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -269,6 +269,28 @@ sdhc_1: sdhci@f9824900 { status = "disabled"; }; + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -573,6 +595,42 @@ i2c13_sleep: i2c13-sleep { drive-strength = <2>; bias-disable; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/9] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio 2020-07-28 12:00 ` [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 3/9] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen Konrad Dybcio ` (6 subsequent siblings) 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This will be required to support touchscreen on Lumia devices. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 9b42ac42b171..c7dc81311f6a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -304,6 +304,27 @@ blsp1_uart2: serial@f991e000 { status = "disabled"; }; + /* + * This I2C seems to only be present on WP platforms + * and is likely disabled in firmware + * (hangs at least one device) on android platforms. + */ + blsp_i2c1: i2c@f9923000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9923000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; @@ -524,6 +545,20 @@ sdc1_rclk_off: rclk-off { bias-pull-down; }; + i2c1_default: i2c1-default { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + function = "gpio"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + i2c2_default: i2c2-default { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/9] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio 2020-07-28 12:00 ` [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 Konrad Dybcio 2020-07-28 12:00 ` [PATCH 2/9] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 4/9] arm64: dts: qcom: msm8994: Add USB support Konrad Dybcio ` (5 subsequent siblings) 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This adds touchscreen capabilities to the Lumia 950. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- .../dts/qcom/msm8992-msft-lumia-talkman.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts index 3cc01f02219d..c337a86a5c77 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -32,6 +32,34 @@ chosen { }; }; +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2560>; + }; + }; +}; + &sdhc_1 { status = "okay"; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/9] arm64: dts: qcom: msm8994: Add USB support 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (2 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 3/9] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 5/9] arm64: dts: qcom: msm8992: " Konrad Dybcio ` (4 subsequent siblings) 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6707f898607f..69c99a4cd817 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -282,6 +282,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/9] arm64: dts: qcom: msm8992: Add USB support 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (3 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 4/9] arm64: dts: qcom: msm8994: Add USB support Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs Konrad Dybcio ` (3 subsequent siblings) 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c7dc81311f6a..c9502fcf5d70 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -242,6 +242,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (4 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 5/9] arm64: dts: qcom: msm8992: " Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-29 1:23 ` Stephen Boyd 2020-07-28 12:00 ` [PATCH 7/9] arm64: dts: qcom: kitakami: Add Synaptics touchscreen Konrad Dybcio ` (2 subsequent siblings) 8 siblings, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- I plan on converting this to use parent_data later on, but I think we could merge it as-is for now..? drivers/clk/qcom/gcc-msm8994.c | 388 ++++++++++++++++++- include/dt-bindings/clock/qcom,gcc-msm8994.h | 36 ++ 2 files changed, 423 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index b7fc8c7ba195..144d2ba7a9be 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -20,6 +20,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -1772,6 +1773,32 @@ static struct clk_branch gcc_gp3_clk = { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg = 0x0280, + .clkr = { + .enable_reg = 0x0280, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_lpass_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x0284, + .clkr = { + .enable_reg = 0x0284, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_aux_clk = { .halt_reg = 0x1ad4, .clkr = { @@ -1790,6 +1817,32 @@ static struct clk_branch gcc_pcie_0_aux_clk = { }, }; +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .halt_reg = 0x1ad0, + .clkr = { + .enable_reg = 0x1ad0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .halt_reg = 0x1acc, + .clkr = { + .enable_reg = 0x1acc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x1ad8, .halt_check = BRANCH_HALT_DELAY, @@ -1809,6 +1862,20 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .halt_reg = 0x1ac8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1ac8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_aux_clk = { .halt_reg = 0x1b54, .clkr = { @@ -1827,6 +1894,32 @@ static struct clk_branch gcc_pcie_1_aux_clk = { }, }; +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .halt_reg = 0x1b54, + .clkr = { + .enable_reg = 0x1b54, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .halt_reg = 0x1b50, + .clkr = { + .enable_reg = 0x1b50, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x1b58, .halt_check = BRANCH_HALT_DELAY, @@ -1846,6 +1939,19 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .halt_reg = 0x1b48, + .clkr = { + .enable_reg = 0x1b48, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x0ccc, .clkr = { @@ -1864,6 +1970,19 @@ static struct clk_branch gcc_pdm2_clk = { }, }; +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x0cc4, + .clkr = { + .enable_reg = 0x0cc4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc1_apps_clk = { .halt_reg = 0x04c4, .clkr = { @@ -1899,6 +2018,23 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { }, }; +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x0508, + .clkr = { + .enable_reg = 0x0508, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc2_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc2_apps_clk = { .halt_reg = 0x0504, .clkr = { @@ -1917,6 +2053,23 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; +static struct clk_branch gcc_sdcc3_ahb_clk = { + .halt_reg = 0x0548, + .clkr = { + .enable_reg = 0x0548, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc3_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc3_apps_clk = { .halt_reg = 0x0544, .clkr = { @@ -1935,6 +2088,23 @@ static struct clk_branch gcc_sdcc3_apps_clk = { }, }; +static struct clk_branch gcc_sdcc4_ahb_clk = { + .halt_reg = 0x0588, + .clkr = { + .enable_reg = 0x0588, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc4_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc4_apps_clk = { .halt_reg = 0x0584, .clkr = { @@ -1989,6 +2159,19 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { }, }; +static struct clk_branch gcc_tsif_ahb_clk = { + .halt_reg = 0x0d84, + .clkr = { + .enable_reg = 0x0d84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_tsif_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_tsif_ref_clk = { .halt_reg = 0x0d88, .clkr = { @@ -2007,6 +2190,19 @@ static struct clk_branch gcc_tsif_ref_clk = { }, }; +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x1d4c, + .clkr = { + .enable_reg = 0x1d4c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_axi_clk = { .halt_reg = 0x1d48, .clkr = { @@ -2043,6 +2239,34 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_rx_symbol_0_clk = { + .halt_reg = 0x1d60, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d60, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_rx_symbol_1_clk = { + .halt_reg = 0x1d64, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d64, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_tx_cfg_clk = { .halt_reg = 0x1d50, .clkr = { @@ -2061,6 +2285,47 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_tx_symbol_0_clk = { + .halt_reg = 0x1d58, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d58, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_tx_symbol_1_clk = { + .halt_reg = 0x1d5c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d5c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { + .halt_reg = 0x04ac, + .clkr = { + .enable_reg = 0x04ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb2_hs_phy_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb30_master_clk = { .halt_reg = 0x03c8, .clkr = { @@ -2097,6 +2362,19 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { }, }; +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0x03cc, + .clkr = { + .enable_reg = 0x03cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_phy_aux_clk = { .halt_reg = 0x1408, .clkr = { @@ -2115,6 +2393,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb_hs_ahb_clk = { + .halt_reg = 0x0488, + .clkr = { + .enable_reg = 0x0488, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_hs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb_hs_system_clk = { .halt_reg = 0x0484, .clkr = { @@ -2133,6 +2424,59 @@ static struct clk_branch gcc_usb_hs_system_clk = { }, }; +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x1a84, + .clkr = { + .enable_reg = 0x1a84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc pcie_gdsc = { + .gdscr = 0x1e18, + .pd = { + .name = "pcie", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie_0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie_1", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x3c4, + .pd = { + .name = "usb30", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_gdsc = { + .gdscr = 0x1d44, + .pd = { + .name = "ufs", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_msm8994_clocks[] = { [GPLL0_EARLY] = &gpll0_early.clkr, [GPLL0] = &gpll0.clkr, @@ -2233,26 +2577,64 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, + [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, + [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, +}; + +static struct gdsc *gcc_msm8994_gdscs[] = { + [PCIE_GDSC] = &pcie_gdsc, + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, + [USB30_GDSC] = &usb30_gdsc, + [UFS_GDSC] = &ufs_gdsc, +}; + +static const struct qcom_reset_map gcc_msm8994_resets[] = { + [USB3_PHY_RESET] = { 0x1400 }, + [USB3PHY_PHY_RESET] = { 0x1404 }, + [PCIE_PHY_0_RESET] = { 0x1b18 }, + [PCIE_PHY_1_RESET] = { 0x1b98 }, + [QUSB2_PHY_RESET] = { 0x04b8 }, }; static const struct regmap_config gcc_msm8994_regmap_config = { @@ -2267,6 +2649,10 @@ static const struct qcom_cc_desc gcc_msm8994_desc = { .config = &gcc_msm8994_regmap_config, .clks = gcc_msm8994_clocks, .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), + .resets = gcc_msm8994_resets, + .num_resets = ARRAY_SIZE(gcc_msm8994_resets), + .gdscs = gcc_msm8994_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), }; static const struct of_device_id gcc_msm8994_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 938969309e00..507b8d6effd2 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -126,5 +126,41 @@ #define GCC_USB3_PHY_AUX_CLK 116 #define GCC_USB_HS_SYSTEM_CLK 117 #define GCC_SDCC1_AHB_CLK 118 +#define GCC_LPASS_Q6_AXI_CLK 119 +#define GCC_MSS_Q6_BIMC_AXI_CLK 120 +#define GCC_PCIE_0_CFG_AHB_CLK 121 +#define GCC_PCIE_0_MSTR_AXI_CLK 122 +#define GCC_PCIE_0_SLV_AXI_CLK 123 +#define GCC_PCIE_1_CFG_AHB_CLK 124 +#define GCC_PCIE_1_MSTR_AXI_CLK 125 +#define GCC_PCIE_1_SLV_AXI_CLK 126 +#define GCC_PDM_AHB_CLK 127 +#define GCC_SDCC2_AHB_CLK 128 +#define GCC_SDCC3_AHB_CLK 129 +#define GCC_SDCC4_AHB_CLK 130 +#define GCC_TSIF_AHB_CLK 131 +#define GCC_UFS_AHB_CLK 132 +#define GCC_UFS_RX_SYMBOL_0_CLK 133 +#define GCC_UFS_RX_SYMBOL_1_CLK 134 +#define GCC_UFS_TX_SYMBOL_0_CLK 135 +#define GCC_UFS_TX_SYMBOL_1_CLK 136 +#define GCC_USB2_HS_PHY_SLEEP_CLK 137 +#define GCC_USB30_SLEEP_CLK 138 +#define GCC_USB_HS_AHB_CLK 139 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 + +/* GDSCs */ +#define PCIE_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define USB30_GDSC 3 +#define UFS_GDSC 4 + +/* Resets */ +#define USB3_PHY_RESET 0 +#define USB3PHY_PHY_RESET 1 +#define PCIE_PHY_0_RESET 2 +#define PCIE_PHY_1_RESET 3 +#define QUSB2_PHY_RESET 4 #endif -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs 2020-07-28 12:00 ` [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs Konrad Dybcio @ 2020-07-29 1:23 ` Stephen Boyd 0 siblings, 0 replies; 11+ messages in thread From: Stephen Boyd @ 2020-07-29 1:23 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, linux-arm-msm, devicetree, linux-kernel, linux-clk Quoting Konrad Dybcio (2020-07-28 05:00:45) > This change adds GDSCs, resets and most of the missing > clocks to the msm8994 GCC driver. The remaining ones > are of local_vote_clk and gate_clk type, which are not > yet supported upstream. Also reorder them to match the > original downstream driver. > > Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> > --- > I plan on converting this to use parent_data later on, > but I think we could merge it as-is for now..? Why not convert to parent_data now? Otherwise we can wait given that the merge window is near anyway. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 7/9] arm64: dts: qcom: kitakami: Add Synaptics touchscreen 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (5 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 8/9] arm64: dts: qcom: msm8994: Add SDHCI2 node Konrad Dybcio 2020-07-28 12:00 ` [PATCH 9/9] arm64: dts: qcom: kitakami: Enable SDHCI2 Konrad Dybcio 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk All Kitakami devices seem to use the Synaptics RMI4 touchscreen attached to the same i2c bus. Configure and enable it. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 4032b7478f04..696cd39852f4 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -138,7 +138,34 @@ &blsp_i2c5 { &blsp_i2c6 { status = "okay"; - /* Synaptics touchscreen */ + rmi4-i2c-dev@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + vdd-supply = <&pm8994_l22>; + vio-supply = <&pm8994_s4>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <220>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; }; &blsp1_uart2 { @@ -233,3 +260,19 @@ &sdhc1 { * vqmmc-supply = <&pm8994_s4>; */ }; + +&tlmm { + ts_int_active: ts-int-active { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + ts_reset_active: ts-reset-active { + pins = "gpio109"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 8/9] arm64: dts: qcom: msm8994: Add SDHCI2 node 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (6 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 7/9] arm64: dts: qcom: kitakami: Add Synaptics touchscreen Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 2020-07-28 12:00 ` [PATCH 9/9] arm64: dts: qcom: kitakami: Enable SDHCI2 Konrad Dybcio 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk Add SDHCI2 to enable use of uSD cards on msm8994. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 69c99a4cd817..58fc8b0321c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -336,6 +336,28 @@ sdhc1: sdhci@f9824900 { status = "disabled"; }; + sdhc2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_dma: dma@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; @@ -714,6 +736,42 @@ sdc1_rclk_off: rclk-off { pins = "sdc1_rclk"; bias-pull-down; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <10>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 9/9] arm64: dts: qcom: kitakami: Enable SDHCI2 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio ` (7 preceding siblings ...) 2020-07-28 12:00 ` [PATCH 8/9] arm64: dts: qcom: msm8994: Add SDHCI2 node Konrad Dybcio @ 2020-07-28 12:00 ` Konrad Dybcio 8 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2020-07-28 12:00 UTC (permalink / raw) To: konradybcio Cc: lauren.kelly, Andy Gross, Bjorn Andersson, Rob Herring, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel, linux-clk This enables the use of uSD cards. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 696cd39852f4..806e8ee00833 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -261,6 +261,10 @@ &sdhc1 { */ }; +&sdhc2 { + status = "okay"; +}; + &tlmm { ts_int_active: ts-int-active { pins = "gpio42"; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-29 1:23 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-28 12:00 [PATCH 0/9] msm8992/4 updates Konrad Dybcio 2020-07-28 12:00 ` [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 Konrad Dybcio 2020-07-28 12:00 ` [PATCH 2/9] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support Konrad Dybcio 2020-07-28 12:00 ` [PATCH 3/9] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen Konrad Dybcio 2020-07-28 12:00 ` [PATCH 4/9] arm64: dts: qcom: msm8994: Add USB support Konrad Dybcio 2020-07-28 12:00 ` [PATCH 5/9] arm64: dts: qcom: msm8992: " Konrad Dybcio 2020-07-28 12:00 ` [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs Konrad Dybcio 2020-07-29 1:23 ` Stephen Boyd 2020-07-28 12:00 ` [PATCH 7/9] arm64: dts: qcom: kitakami: Add Synaptics touchscreen Konrad Dybcio 2020-07-28 12:00 ` [PATCH 8/9] arm64: dts: qcom: msm8994: Add SDHCI2 node Konrad Dybcio 2020-07-28 12:00 ` [PATCH 9/9] arm64: dts: qcom: kitakami: Enable SDHCI2 Konrad Dybcio
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