arch/mips/include/asm/fpu.h:79 __enable_fpu() warn: ignoring unreachable code.

arch/mips/include/asm/fpu.h:79 __enable_fpu() warn: ignoring unreachable code.

[kernel test robot]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   06a4ec1d9dc652e17ee3ac2ceb6c7cf6c2b75cdd
commit: c9b0299034665d594e56ee343f28033d1b24de6d MIPS: Use fallthrough for arch/mips
date:   3 months ago
config: mips-randconfig-m031-20200818 (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

New smatch warnings:
arch/mips/include/asm/fpu.h:79 __enable_fpu() warn: ignoring unreachable code.
arch/mips/include/asm/fpu.h:79 __enable_fpu() warn: ignoring unreachable code.

Old smatch warnings:
arch/mips/kernel/traps.c:1914 nmi_exception_handler() warn: ignoring unreachable code.

# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c9b0299034665d594e56ee343f28033d1b24de6d
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout c9b0299034665d594e56ee343f28033d1b24de6d
vim +79 arch/mips/include/asm/fpu.h

    53	
    54	static inline int __enable_fpu(enum fpu_mode mode)
    55	{
    56		int fr;
    57	
    58		switch (mode) {
    59		case FPU_AS_IS:
    60			/* just enable the FPU in its current mode */
    61			set_c0_status(ST0_CU1);
    62			enable_fpu_hazard();
    63			return 0;
    64	
    65		case FPU_HYBRID:
    66			if (!cpu_has_fre)
    67				return SIGFPE;
    68	
    69			/* set FRE */
    70			set_c0_config5(MIPS_CONF5_FRE);
    71			goto fr_common;
    72	
    73		case FPU_64BIT:
    74	#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
    75	      || defined(CONFIG_64BIT))
    76			/* we only have a 32-bit FPU */
    77			return SIGFPE;
    78	#endif
  > 79			fallthrough;
    80		case FPU_32BIT:
    81			if (cpu_has_fre) {
    82				/* clear FRE */
    83				clear_c0_config5(MIPS_CONF5_FRE);
    84			}
    85	fr_common:
    86			/* set CU1 & change FR appropriately */
    87			fr = (int)mode & FPU_FR_MASK;
    88			change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
    89			enable_fpu_hazard();
    90	
    91			/* check FR has the desired value */
    92			if (!!(read_c0_status() & ST0_FR) == !!fr)
    93				return 0;
    94	
    95			/* unsupported FR value */
    96			__disable_fpu();
    97			return SIGFPE;
    98	
    99		default:
   100			BUG();
   101		}
   102	
   103		return SIGFPE;
   104	}
   105	

---
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