* [PATCH RESEND 0/2] Fix cacheinfo @ 2020-08-20 0:42 Jiaxun Yang 2020-08-20 0:42 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang 2020-08-21 16:57 ` [PATCH RESEND 0/2] Fix cacheinfo Thomas Bogendoerfer 0 siblings, 2 replies; 6+ messages in thread From: Jiaxun Yang @ 2020-08-20 0:42 UTC (permalink / raw) To: linux-mips Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel This is causing lscpu segfault. So probably worthy to include it as a part of mips-fixes. Jiaxun Yang (2): MIPS: cacheinfo: Add missing VCache MIPS: Loongson64: Set cluster for cores arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- arch/mips/loongson64/smp.c | 2 ++ 2 files changed, 28 insertions(+), 8 deletions(-) -- 2.28.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache 2020-08-20 0:42 [PATCH RESEND 0/2] Fix cacheinfo Jiaxun Yang @ 2020-08-20 0:42 ` Jiaxun Yang 2020-08-21 16:55 ` Thomas Bogendoerfer 2020-08-21 16:57 ` [PATCH RESEND 0/2] Fix cacheinfo Thomas Bogendoerfer 1 sibling, 1 reply; 6+ messages in thread From: Jiaxun Yang @ 2020-08-20 0:42 UTC (permalink / raw) To: linux-mips Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel Victim Cache is defined by Loongson as per-core unified private Cache. Add this into cacheinfo and make cache levels selfincrement instead of hardcode levels. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c index 47312c529410..83548331ee94 100644 --- a/arch/mips/kernel/cacheinfo.c +++ b/arch/mips/kernel/cacheinfo.c @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu) leaves += (c->icache.waysize) ? 2 : 1; + if (c->vcache.waysize) { + levels++; + leaves++; + } + if (c->scache.waysize) { levels++; leaves++; @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu) struct cpuinfo_mips *c = ¤t_cpu_data; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); struct cacheinfo *this_leaf = this_cpu_ci->info_list; + int level = 1; if (c->icache.waysize) { - /* L1 caches are per core */ + /* D/I caches are per core */ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); + level++; } else { - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; + } + + if (c->vcache.waysize) { + /* Vcache is per core as well */ + fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); + populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; } if (c->scache.waysize) { - /* L2 cache is per cluster */ + /* Scache is per cluster */ fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map); - populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED); + populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; } - if (c->tcache.waysize) - populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); + if (c->tcache.waysize) { + populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; + } this_cpu_ci->cpu_map_populated = true; -- 2.28.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache 2020-08-20 0:42 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang @ 2020-08-21 16:55 ` Thomas Bogendoerfer 2020-11-03 5:40 ` Jiaxun Yang 0 siblings, 1 reply; 6+ messages in thread From: Thomas Bogendoerfer @ 2020-08-21 16:55 UTC (permalink / raw) To: Jiaxun Yang Cc: linux-mips, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote: > Victim Cache is defined by Loongson as per-core unified > private Cache. > Add this into cacheinfo and make cache levels selfincrement > instead of hardcode levels. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- > 1 file changed, 26 insertions(+), 8 deletions(-) > > diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c > index 47312c529410..83548331ee94 100644 > --- a/arch/mips/kernel/cacheinfo.c > +++ b/arch/mips/kernel/cacheinfo.c > @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu) > > leaves += (c->icache.waysize) ? 2 : 1; > > + if (c->vcache.waysize) { > + levels++; > + leaves++; > + } > + > if (c->scache.waysize) { > levels++; > leaves++; > @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu) > struct cpuinfo_mips *c = ¤t_cpu_data; > struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); > struct cacheinfo *this_leaf = this_cpu_ci->info_list; > + int level = 1; > > if (c->icache.waysize) { > - /* L1 caches are per core */ > + /* D/I caches are per core */ > fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); > - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); > + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); > fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); > - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); > + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); > + level++; > } else { > - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); > + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED); > + level++; > + } > + > + if (c->vcache.waysize) { why can't we insert vcache as level 4 and leave the rest of the file alone ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache 2020-08-21 16:55 ` Thomas Bogendoerfer @ 2020-11-03 5:40 ` Jiaxun Yang 2020-11-25 8:15 ` Tiezhu Yang 0 siblings, 1 reply; 6+ messages in thread From: Jiaxun Yang @ 2020-11-03 5:40 UTC (permalink / raw) To: Thomas Bogendoerfer Cc: linux-mips, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel 在 2020/8/22 0:55, Thomas Bogendoerfer 写道: > On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote: >> Victim Cache is defined by Loongson as per-core unified >> private Cache. >> Add this into cacheinfo and make cache levels selfincrement >> instead of hardcode levels. >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> --- >> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- >> 1 file changed, 26 insertions(+), 8 deletions(-) >> >> diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c >> index 47312c529410..83548331ee94 100644 >> --- a/arch/mips/kernel/cacheinfo.c >> +++ b/arch/mips/kernel/cacheinfo.c >> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu) >> >> leaves += (c->icache.waysize) ? 2 : 1; >> >> + if (c->vcache.waysize) { >> + levels++; >> + leaves++; >> + } >> + >> if (c->scache.waysize) { >> levels++; >> leaves++; >> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu) >> struct cpuinfo_mips *c = ¤t_cpu_data; >> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); >> struct cacheinfo *this_leaf = this_cpu_ci->info_list; >> + int level = 1; >> >> if (c->icache.waysize) { >> - /* L1 caches are per core */ >> + /* D/I caches are per core */ >> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); >> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); >> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); >> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); >> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); >> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); >> + level++; >> } else { >> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); >> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED); >> + level++; >> + } >> + >> + if (c->vcache.waysize) { > why can't we insert vcache as level 4 and leave the rest of the file > alone ? Hi Thomas, Oops I forgot this patch. Because VCache is physicaly placed between Scache and I/D Cache as per core chahe, it will confuse userspace program otherwise. Also I do think the level should be continues. Thanks - Jiaxun > > Thomas. > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache 2020-11-03 5:40 ` Jiaxun Yang @ 2020-11-25 8:15 ` Tiezhu Yang 0 siblings, 0 replies; 6+ messages in thread From: Tiezhu Yang @ 2020-11-25 8:15 UTC (permalink / raw) To: Jiaxun Yang, Thomas Bogendoerfer Cc: linux-mips, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel, Xuefeng Li On 11/03/2020 01:40 PM, Jiaxun Yang wrote: > > > 在 2020/8/22 0:55, Thomas Bogendoerfer 写道: >> On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote: >>> Victim Cache is defined by Loongson as per-core unified >>> private Cache. >>> Add this into cacheinfo and make cache levels selfincrement >>> instead of hardcode levels. >>> >>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >>> --- >>> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- >>> 1 file changed, 26 insertions(+), 8 deletions(-) >>> >>> diff --git a/arch/mips/kernel/cacheinfo.c >>> b/arch/mips/kernel/cacheinfo.c >>> index 47312c529410..83548331ee94 100644 >>> --- a/arch/mips/kernel/cacheinfo.c >>> +++ b/arch/mips/kernel/cacheinfo.c >>> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu) >>> leaves += (c->icache.waysize) ? 2 : 1; >>> + if (c->vcache.waysize) { >>> + levels++; >>> + leaves++; >>> + } >>> + >>> if (c->scache.waysize) { >>> levels++; >>> leaves++; >>> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int >>> cpu) >>> struct cpuinfo_mips *c = ¤t_cpu_data; >>> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); >>> struct cacheinfo *this_leaf = this_cpu_ci->info_list; >>> + int level = 1; >>> if (c->icache.waysize) { >>> - /* L1 caches are per core */ >>> + /* D/I caches are per core */ >>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); >>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); >>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); >>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); >>> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); >>> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); >>> + level++; >>> } else { >>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); >>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED); >>> + level++; >>> + } >>> + >>> + if (c->vcache.waysize) { >> why can't we insert vcache as level 4 and leave the rest of the file >> alone ? > > Hi Thomas, > > Oops I forgot this patch. > > Because VCache is physicaly placed between Scache and I/D Cache as per > core chahe, it will confuse userspace program otherwise. > > Also I do think the level should be continues. With this patch, we can see the vcache info as L2 cache and scache info as L3 cache on the Loongson 3A3000 and 3A4000 platform. Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn> > > Thanks > > - Jiaxun > >> >> Thomas. >> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RESEND 0/2] Fix cacheinfo 2020-08-20 0:42 [PATCH RESEND 0/2] Fix cacheinfo Jiaxun Yang 2020-08-20 0:42 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang @ 2020-08-21 16:57 ` Thomas Bogendoerfer 1 sibling, 0 replies; 6+ messages in thread From: Thomas Bogendoerfer @ 2020-08-21 16:57 UTC (permalink / raw) To: Jiaxun Yang Cc: linux-mips, Huacai Chen, Vladimir Kondratiev, Paul Burton, linux-kernel On Thu, Aug 20, 2020 at 08:42:48AM +0800, Jiaxun Yang wrote: > This is causing lscpu segfault. So probably worthy to > include it as a part of mips-fixes. > > Jiaxun Yang (2): > MIPS: cacheinfo: Add missing VCache > MIPS: Loongson64: Set cluster for cores I've only received one patch and there I can't see why lscpu will crash since it's just missing information. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-25 8:15 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-20 0:42 [PATCH RESEND 0/2] Fix cacheinfo Jiaxun Yang 2020-08-20 0:42 ` [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache Jiaxun Yang 2020-08-21 16:55 ` Thomas Bogendoerfer 2020-11-03 5:40 ` Jiaxun Yang 2020-11-25 8:15 ` Tiezhu Yang 2020-08-21 16:57 ` [PATCH RESEND 0/2] Fix cacheinfo Thomas Bogendoerfer
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