* [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables
@ 2020-08-22 16:32 Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Krzysztof Kozlowski
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2020-08-22 16:32 UTC (permalink / raw)
To: Lukasz Luba, Krzysztof Kozlowski, Kukjin Kim, linux-pm,
linux-samsung-soc, linux-kernel, linux-arm-kernel
The driver has file-scope arrays defining fields of timing registers
(e.g. struct timing_reg timing_row) and actual values for these
registers per each OPP in state container (struct
exynos5_dmc.timing_row). The meanings of these are different so use
different names to avoid confusion.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/memory/samsung/exynos5422-dmc.c | 49 +++++++++++++------------
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 0045fa536b2b..31864ce59b25 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -170,7 +170,7 @@ struct timing_reg {
unsigned int val;
};
-static const struct timing_reg timing_row[] = {
+static const struct timing_reg timing_row_reg_fields[] = {
TIMING_FIELD("tRFC", 24, 31),
TIMING_FIELD("tRRD", 20, 23),
TIMING_FIELD("tRP", 16, 19),
@@ -179,7 +179,7 @@ static const struct timing_reg timing_row[] = {
TIMING_FIELD("tRAS", 0, 5),
};
-static const struct timing_reg timing_data[] = {
+static const struct timing_reg timing_data_reg_fields[] = {
TIMING_FIELD("tWTR", 28, 31),
TIMING_FIELD("tWR", 24, 27),
TIMING_FIELD("tRTP", 20, 23),
@@ -190,7 +190,7 @@ static const struct timing_reg timing_data[] = {
TIMING_FIELD("RL", 0, 3),
};
-static const struct timing_reg timing_power[] = {
+static const struct timing_reg timing_power_reg_fields[] = {
TIMING_FIELD("tFAW", 26, 31),
TIMING_FIELD("tXSR", 16, 25),
TIMING_FIELD("tXP", 8, 15),
@@ -198,8 +198,9 @@ static const struct timing_reg timing_power[] = {
TIMING_FIELD("tMRD", 0, 3),
};
-#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
- ARRAY_SIZE(timing_power))
+#define TIMING_COUNT (ARRAY_SIZE(timing_row_reg_fields) + \
+ ARRAY_SIZE(timing_data_reg_fields) + \
+ ARRAY_SIZE(timing_power_reg_fields))
static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
{
@@ -1022,117 +1023,117 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
val = dmc->timings->tRFC / clk_period_ps;
val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRFC);
- reg = &timing_row[0];
+ reg = &timing_row_reg_fields[0];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRRD / clk_period_ps;
val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRRD);
- reg = &timing_row[1];
+ reg = &timing_row_reg_fields[1];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRPab / clk_period_ps;
val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRPab);
- reg = &timing_row[2];
+ reg = &timing_row_reg_fields[2];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRCD / clk_period_ps;
val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRCD);
- reg = &timing_row[3];
+ reg = &timing_row_reg_fields[3];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRC / clk_period_ps;
val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRC);
- reg = &timing_row[4];
+ reg = &timing_row_reg_fields[4];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRAS / clk_period_ps;
val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRAS);
- reg = &timing_row[5];
+ reg = &timing_row_reg_fields[5];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
/* data related timings */
val = dmc->timings->tWTR / clk_period_ps;
val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWTR);
- reg = &timing_data[0];
+ reg = &timing_data_reg_fields[0];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tWR / clk_period_ps;
val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWR);
- reg = &timing_data[1];
+ reg = &timing_data_reg_fields[1];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRTP / clk_period_ps;
val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRTP);
- reg = &timing_data[2];
+ reg = &timing_data_reg_fields[2];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tW2W_C2C / clk_period_ps;
val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tW2W_C2C);
- reg = &timing_data[3];
+ reg = &timing_data_reg_fields[3];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tR2R_C2C / clk_period_ps;
val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tR2R_C2C);
- reg = &timing_data[4];
+ reg = &timing_data_reg_fields[4];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tWL / clk_period_ps;
val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWL);
- reg = &timing_data[5];
+ reg = &timing_data_reg_fields[5];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tDQSCK / clk_period_ps;
val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tDQSCK);
- reg = &timing_data[6];
+ reg = &timing_data_reg_fields[6];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRL / clk_period_ps;
val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRL);
- reg = &timing_data[7];
+ reg = &timing_data_reg_fields[7];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
/* power related timings */
val = dmc->timings->tFAW / clk_period_ps;
val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tFAW);
- reg = &timing_power[0];
+ reg = &timing_power_reg_fields[0];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tXSR / clk_period_ps;
val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tXSR);
- reg = &timing_power[1];
+ reg = &timing_power_reg_fields[1];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tXP / clk_period_ps;
val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tXP);
- reg = &timing_power[2];
+ reg = &timing_power_reg_fields[2];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tCKE / clk_period_ps;
val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tCKE);
- reg = &timing_power[3];
+ reg = &timing_power_reg_fields[3];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tMRD / clk_period_ps;
val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tMRD);
- reg = &timing_power[4];
+ reg = &timing_power_reg_fields[4];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
return 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members
2020-08-22 16:32 [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Krzysztof Kozlowski
@ 2020-08-22 16:32 ` Krzysztof Kozlowski
2020-08-24 11:43 ` Lukasz Luba
2020-08-22 16:32 ` [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc Krzysztof Kozlowski
2020-08-24 10:59 ` [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Lukasz Luba
2 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2020-08-22 16:32 UTC (permalink / raw)
To: Lukasz Luba, Krzysztof Kozlowski, Kukjin Kim, linux-pm,
linux-samsung-soc, linux-kernel, linux-arm-kernel
The struct exynos5_dmc members bypass_rate, mx_mspll_ccore_phy,
mout_mx_mspll_ccore_phy and opp_bypass are not actually used.
Apparently there was a plan to store the OPP for the bypass mode in
opp_bypass member, but drivers fails to do it and instead always sets
target voltage during bypass mode.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/memory/samsung/exynos5422-dmc.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 31864ce59b25..df02afa8aa90 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -123,9 +123,7 @@ struct exynos5_dmc {
struct mutex lock;
unsigned long curr_rate;
unsigned long curr_volt;
- unsigned long bypass_rate;
struct dmc_opp_table *opp;
- struct dmc_opp_table opp_bypass;
int opp_count;
u32 timings_arr_size;
u32 *timing_row;
@@ -143,8 +141,6 @@ struct exynos5_dmc {
struct clk *mout_bpll;
struct clk *mout_mclk_cdrex;
struct clk *mout_mx_mspll_ccore;
- struct clk *mx_mspll_ccore_phy;
- struct clk *mout_mx_mspll_ccore_phy;
struct devfreq_event_dev **counter;
int num_counters;
u64 last_overflow_ts[2];
@@ -455,9 +451,6 @@ static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
unsigned long target_volt)
{
int ret = 0;
- unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
-
- target_volt = max(bypass_volt, target_volt);
if (dmc->curr_volt >= target_volt)
return 0;
@@ -1268,8 +1261,6 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
- dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
-
clk_prepare_enable(dmc->fout_bpll);
clk_prepare_enable(dmc->mout_bpll);
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc
2020-08-22 16:32 [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Krzysztof Kozlowski
@ 2020-08-22 16:32 ` Krzysztof Kozlowski
2020-08-24 11:01 ` Lukasz Luba
2020-08-24 10:59 ` [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Lukasz Luba
2 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2020-08-22 16:32 UTC (permalink / raw)
To: Lukasz Luba, Krzysztof Kozlowski, Kukjin Kim, linux-pm,
linux-samsung-soc, linux-kernel, linux-arm-kernel
Add missing kerneldoc to struct exynos5_dmc and correct the existing
kerneldoc in other places to fix W=1 warnings like:
drivers/memory/samsung/exynos5422-dmc.c:107: warning: Function parameter or member 'freq_hz' not described in 'dmc_opp_table'
drivers/memory/samsung/exynos5422-dmc.c:154: warning: Function parameter or member 'dev' not described in 'exynos5_dmc'
drivers/memory/samsung/exynos5422-dmc.c:357: warning: Excess function parameter 'param' description in 'exynos5_set_bypass_dram_timings'
drivers/memory/samsung/exynos5422-dmc.c:630: warning: Function parameter or member 'flags' not described in 'exynos5_dmc_get_volt_freq'
drivers/memory/samsung/exynos5422-dmc.c:962: warning: cannot understand function prototype: 'struct devfreq_dev_profile exynos5_dmc_df_profile = '
drivers/memory/samsung/exynos5422-dmc.c:1011: warning: Function parameter or member 'reg_timing_row' not described in 'create_timings_aligned'
drivers/memory/samsung/exynos5422-dmc.c:1011: warning: Excess function parameter 'idx' description in 'create_timings_aligned'
drivers/memory/samsung/exynos5422-dmc.c:1345: warning: Excess function parameter 'set' description in 'exynos5_dmc_set_pause_on_switching'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/memory/samsung/exynos5422-dmc.c | 44 ++++++++++++++++++++++---
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index df02afa8aa90..a9d04bd31603 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -108,6 +108,41 @@ struct dmc_opp_table {
/**
* struct exynos5_dmc - main structure describing DMC device
+ * @dev: DMC device
+ * @df: devfreq device structure returned by devfreq framework
+ * @gov_data: configuration of devfreq governor
+ * @base_drexi0: DREX0 registers mapping
+ * @base_drexi1: DREX1 registers mapping
+ * @clk_regmap: regmap for clock controller registers
+ * @lock: protects curr_rate and frequency/voltage setting section
+ * @curr_rate: current frequency
+ * @curr_volt: current voltage
+ * @opp: OPP table
+ * @opp_count: number of 'opp' elements
+ * @timings_arr_size: number of 'timings' elements
+ * @timing_row: values for timing row register, for each OPP
+ * @timing_data: values for timing data register, for each OPP
+ * @timing_power: balues for timing power register, for each OPP
+ * @timings: DDR memory timings, from device tree
+ * @min_tck: DDR memory minimum timing values, from device tree
+ * @bypass_timing_row: value for timing row register for bypass timings
+ * @bypass_timing_data: value for timing data register for bypass timings
+ * @bypass_timing_power: value for timing power register for bypass
+ * timings
+ * @vdd_mif: Memory interface regulator
+ * @fout_spll: clock: SPLL
+ * @fout_bpll: clock: BPLL
+ * @mout_spll: clock: mux SPLL
+ * @mout_bpll: clock: mux BPLL
+ * @mout_mclk_cdrex: clock: mux mclk_cdrex
+ * @mout_mx_mspll_ccore: clock: mux mx_mspll_ccore
+ * @counter: devfreq events
+ * @num_counters: number of 'counter' elements
+ * @last_overflow_ts: time (in ns) of last overflow of each DREX
+ * @load: utilization in percents
+ * @total: total time between devfreq events
+ * @in_irq_mode: whether running in interrupt mode (true)
+ * or polling (false)
*
* The main structure for the Dynamic Memory Controller which covers clocks,
* memory regions, HW information, parameters and current operating mode.
@@ -344,7 +379,6 @@ static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
/**
* exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
* @dmc: device for which the new settings is going to be applied
- * @param: DRAM parameters which passes timing data
*
* Low-level function for changing timings for DRAM memory clocking from
* 'bypass' clock source (fixed frequency @400MHz).
@@ -612,6 +646,7 @@ exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
* requested
* @target_volt: returned voltage which corresponds to the returned
* frequency
+ * @flags: devfreq flags provided for this frequency change request
*
* Function gets requested frequency and checks OPP framework for needed
* frequency and voltage. It populates the values 'target_rate' and
@@ -948,7 +983,7 @@ static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
return 0;
}
-/**
+/*
* exynos5_dmc_df_profile - Devfreq governor's profile structure
*
* It provides to the devfreq framework needed functions and polling period.
@@ -991,7 +1026,9 @@ exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
/**
* create_timings_aligned() - Create register values and align with standard
* @dmc: device for which the frequency is going to be set
- * @idx: speed bin in the OPP table
+ * @reg_timing_row: array to fill with values for timing row register
+ * @reg_timing_data: array to fill with values for timing data register
+ * @reg_timing_power: array to fill with values for timing power register
* @clk_period_ps: the period of the clock, known as tCK
*
* The function calculates timings and creates a register value ready for
@@ -1326,7 +1363,6 @@ static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
/**
* exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
* @dmc: device which is used for changing this feature
- * @set: a boolean state passing enable/disable request
*
* There is a need of pausing DREX DMC when divider or MUX in clock tree
* changes its configuration. In such situation access to the memory is blocked
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables
2020-08-22 16:32 [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc Krzysztof Kozlowski
@ 2020-08-24 10:59 ` Lukasz Luba
2 siblings, 0 replies; 7+ messages in thread
From: Lukasz Luba @ 2020-08-24 10:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, linux-pm, linux-samsung-soc,
linux-kernel, linux-arm-kernel
On 8/22/20 5:32 PM, Krzysztof Kozlowski wrote:
> The driver has file-scope arrays defining fields of timing registers
> (e.g. struct timing_reg timing_row) and actual values for these
> registers per each OPP in state container (struct
> exynos5_dmc.timing_row). The meanings of these are different so use
> different names to avoid confusion.
Good point
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Acked-by: Lukasz Luba <lukasz.luba@arm.com>
Regards,
Lukasz
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc
2020-08-22 16:32 ` [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc Krzysztof Kozlowski
@ 2020-08-24 11:01 ` Lukasz Luba
0 siblings, 0 replies; 7+ messages in thread
From: Lukasz Luba @ 2020-08-24 11:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, linux-pm, linux-samsung-soc,
linux-kernel, linux-arm-kernel
On 8/22/20 5:32 PM, Krzysztof Kozlowski wrote:
> Add missing kerneldoc to struct exynos5_dmc and correct the existing
> kerneldoc in other places to fix W=1 warnings like:
>
> drivers/memory/samsung/exynos5422-dmc.c:107: warning: Function parameter or member 'freq_hz' not described in 'dmc_opp_table'
> drivers/memory/samsung/exynos5422-dmc.c:154: warning: Function parameter or member 'dev' not described in 'exynos5_dmc'
> drivers/memory/samsung/exynos5422-dmc.c:357: warning: Excess function parameter 'param' description in 'exynos5_set_bypass_dram_timings'
> drivers/memory/samsung/exynos5422-dmc.c:630: warning: Function parameter or member 'flags' not described in 'exynos5_dmc_get_volt_freq'
> drivers/memory/samsung/exynos5422-dmc.c:962: warning: cannot understand function prototype: 'struct devfreq_dev_profile exynos5_dmc_df_profile = '
> drivers/memory/samsung/exynos5422-dmc.c:1011: warning: Function parameter or member 'reg_timing_row' not described in 'create_timings_aligned'
> drivers/memory/samsung/exynos5422-dmc.c:1011: warning: Excess function parameter 'idx' description in 'create_timings_aligned'
> drivers/memory/samsung/exynos5422-dmc.c:1345: warning: Excess function parameter 'set' description in 'exynos5_dmc_set_pause_on_switching'
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Lukasz Luba <lukasz.luba@arm.com>
Regards,
Lukasz
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members
2020-08-22 16:32 ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Krzysztof Kozlowski
@ 2020-08-24 11:43 ` Lukasz Luba
2020-08-24 12:01 ` Krzysztof Kozlowski
0 siblings, 1 reply; 7+ messages in thread
From: Lukasz Luba @ 2020-08-24 11:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, linux-pm, linux-samsung-soc,
linux-kernel, linux-arm-kernel
Hi Krzysztof,
On 8/22/20 5:32 PM, Krzysztof Kozlowski wrote:
> The struct exynos5_dmc members bypass_rate, mx_mspll_ccore_phy,
> mout_mx_mspll_ccore_phy and opp_bypass are not actually used.
>
> Apparently there was a plan to store the OPP for the bypass mode in
> opp_bypass member, but drivers fails to do it and instead always sets
> target voltage during bypass mode.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> drivers/memory/samsung/exynos5422-dmc.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
> index 31864ce59b25..df02afa8aa90 100644
> --- a/drivers/memory/samsung/exynos5422-dmc.c
> +++ b/drivers/memory/samsung/exynos5422-dmc.c
> @@ -123,9 +123,7 @@ struct exynos5_dmc {
> struct mutex lock;
> unsigned long curr_rate;
> unsigned long curr_volt;
> - unsigned long bypass_rate;
> struct dmc_opp_table *opp;
> - struct dmc_opp_table opp_bypass;
> int opp_count;
> u32 timings_arr_size;
> u32 *timing_row;
> @@ -143,8 +141,6 @@ struct exynos5_dmc {
> struct clk *mout_bpll;
> struct clk *mout_mclk_cdrex;
> struct clk *mout_mx_mspll_ccore;
> - struct clk *mx_mspll_ccore_phy;
> - struct clk *mout_mx_mspll_ccore_phy;
> struct devfreq_event_dev **counter;
> int num_counters;
> u64 last_overflow_ts[2];
> @@ -455,9 +451,6 @@ static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
> unsigned long target_volt)
> {
> int ret = 0;
> - unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
> -
> - target_volt = max(bypass_volt, target_volt);
Could you explain which use cases you considered when you decided to
remove these lines?
Regards,
Lukasz
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members
2020-08-24 11:43 ` Lukasz Luba
@ 2020-08-24 12:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2020-08-24 12:01 UTC (permalink / raw)
To: Lukasz Luba
Cc: Kukjin Kim, linux-pm, linux-samsung-soc, linux-kernel, linux-arm-kernel
On Mon, Aug 24, 2020 at 12:43:33PM +0100, Lukasz Luba wrote:
> Hi Krzysztof,
>
> On 8/22/20 5:32 PM, Krzysztof Kozlowski wrote:
> > The struct exynos5_dmc members bypass_rate, mx_mspll_ccore_phy,
> > mout_mx_mspll_ccore_phy and opp_bypass are not actually used.
> >
> > Apparently there was a plan to store the OPP for the bypass mode in
> > opp_bypass member, but drivers fails to do it and instead always sets
> > target voltage during bypass mode.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> > ---
> > drivers/memory/samsung/exynos5422-dmc.c | 9 ---------
> > 1 file changed, 9 deletions(-)
> >
> > diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
> > index 31864ce59b25..df02afa8aa90 100644
> > --- a/drivers/memory/samsung/exynos5422-dmc.c
> > +++ b/drivers/memory/samsung/exynos5422-dmc.c
> > @@ -123,9 +123,7 @@ struct exynos5_dmc {
> > struct mutex lock;
> > unsigned long curr_rate;
> > unsigned long curr_volt;
> > - unsigned long bypass_rate;
> > struct dmc_opp_table *opp;
> > - struct dmc_opp_table opp_bypass;
> > int opp_count;
> > u32 timings_arr_size;
> > u32 *timing_row;
> > @@ -143,8 +141,6 @@ struct exynos5_dmc {
> > struct clk *mout_bpll;
> > struct clk *mout_mclk_cdrex;
> > struct clk *mout_mx_mspll_ccore;
> > - struct clk *mx_mspll_ccore_phy;
> > - struct clk *mout_mx_mspll_ccore_phy;
> > struct devfreq_event_dev **counter;
> > int num_counters;
> > u64 last_overflow_ts[2];
> > @@ -455,9 +451,6 @@ static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
> > unsigned long target_volt)
> > {
> > int ret = 0;
> > - unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
> > -
> > - target_volt = max(bypass_volt, target_volt);
>
>
> Could you explain which use cases you considered when you decided to
> remove these lines?
There are no use cases attached to these. These are simply not used,
never assigned a value. For example max(0, target_volt) is always equal
to target_volt for unsigned numbers...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-08-24 12:02 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-22 16:32 [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 2/3] memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members Krzysztof Kozlowski
2020-08-24 11:43 ` Lukasz Luba
2020-08-24 12:01 ` Krzysztof Kozlowski
2020-08-22 16:32 ` [PATCH 3/3] memory: samsung: exynos5422-dmc: add missing and fix kerneldoc Krzysztof Kozlowski
2020-08-24 11:01 ` Lukasz Luba
2020-08-24 10:59 ` [PATCH 1/3] memory: samsung: exynos5422-dmc: rename timing register fields variables Lukasz Luba
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).