* [PATCH 0/2] r8a774e1 add fdp1 and cpuidle support @ 2020-08-27 14:53 Lad Prabhakar 2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar 2020-08-27 14:53 ` [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Lad Prabhakar 0 siblings, 2 replies; 6+ messages in thread From: Lad Prabhakar @ 2020-08-27 14:53 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring Cc: linux-renesas-soc, devicetree, linux-kernel, Lad Prabhakar, Prabhakar Hi All, This series adds support for FDP1 and cpuidle support to R8A774E1 (RZ/G2H) SoC. Cheers, Prabhakar Lad Prabhakar (1): arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Marian-Cristian Rotariu (1): arm64: dts: renesas: r8a774e1: Add FDP1 device nodes arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes 2020-08-27 14:53 [PATCH 0/2] r8a774e1 add fdp1 and cpuidle support Lad Prabhakar @ 2020-08-27 14:53 ` Lad Prabhakar 2020-09-03 12:31 ` Geert Uytterhoeven 2020-09-04 10:33 ` Kieran Bingham 2020-08-27 14:53 ` [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Lad Prabhakar 1 sibling, 2 replies; 6+ messages in thread From: Lad Prabhakar @ 2020-08-27 14:53 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring Cc: linux-renesas-soc, devicetree, linux-kernel, Lad Prabhakar, Prabhakar From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f5909ced7679..34fdb9a0c325 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2504,6 +2504,26 @@ renesas,fcp = <&fcpvi1>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes 2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar @ 2020-09-03 12:31 ` Geert Uytterhoeven 2020-09-04 10:33 ` Kieran Bingham 1 sibling, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 12:31 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar On Thu, Aug 27, 2020 at 4:53 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes 2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar 2020-09-03 12:31 ` Geert Uytterhoeven @ 2020-09-04 10:33 ` Kieran Bingham 1 sibling, 0 replies; 6+ messages in thread From: Kieran Bingham @ 2020-09-04 10:33 UTC (permalink / raw) To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar On 27/08/2020 15:53, Lad Prabhakar wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com> I'd really love to know if people are using this FDP1 with the driver I added ;-) > --- > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > index f5909ced7679..34fdb9a0c325 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2504,6 +2504,26 @@ > renesas,fcp = <&fcpvi1>; > }; > > + fdp1@fe940000 { > + compatible = "renesas,fdp1"; > + reg = <0 0xfe940000 0 0x2400>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 119>; > + power-domains = <&sysc R8A774E1_PD_A3VP>; > + resets = <&cpg 119>; > + renesas,fcp = <&fcpf0>; > + }; > + > + fdp1@fe944000 { > + compatible = "renesas,fdp1"; > + reg = <0 0xfe944000 0 0x2400>; > + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 118>; > + power-domains = <&sysc R8A774E1_PD_A3VP>; > + resets = <&cpg 118>; > + renesas,fcp = <&fcpf1>; > + }; > + > fcpf0: fcp@fe950000 { > compatible = "renesas,fcpf"; > reg = <0 0xfe950000 0 0x200>; > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores 2020-08-27 14:53 [PATCH 0/2] r8a774e1 add fdp1 and cpuidle support Lad Prabhakar 2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar @ 2020-08-27 14:53 ` Lad Prabhakar 2020-09-03 12:39 ` Geert Uytterhoeven 1 sibling, 1 reply; 6+ messages in thread From: Lad Prabhakar @ 2020-08-27 14:53 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring Cc: linux-renesas-soc, devicetree, linux-kernel, Lad Prabhakar, Prabhakar Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 34fdb9a0c325..e5445ba99e84 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -127,6 +127,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -141,6 +142,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -154,6 +156,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -167,6 +170,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -180,6 +184,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; @@ -194,6 +199,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -206,6 +212,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -218,6 +225,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -236,6 +244,28 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal { -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores 2020-08-27 14:53 ` [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Lad Prabhakar @ 2020-09-03 12:39 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 12:39 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar Hi Prabhakar, On Thu, Aug 27, 2020 at 4:53 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -127,6 +127,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > dynamic-power-coefficient = <854>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > @@ -141,6 +142,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -154,6 +156,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -167,6 +170,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; CPU_SLEEP_0 > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -180,6 +184,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > #cooling-cells = <2>; > dynamic-power-coefficient = <277>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > @@ -194,6 +199,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; > @@ -206,6 +212,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; > @@ -218,6 +225,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> No need to resend, will fix while queueing in renesas-devel for v5.10. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-09-04 10:34 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-27 14:53 [PATCH 0/2] r8a774e1 add fdp1 and cpuidle support Lad Prabhakar 2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar 2020-09-03 12:31 ` Geert Uytterhoeven 2020-09-04 10:33 ` Kieran Bingham 2020-08-27 14:53 ` [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Lad Prabhakar 2020-09-03 12:39 ` Geert Uytterhoeven
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