* [PATCH 0/3] Enlarge tracepoints in the display component
@ 2020-09-09 22:53 Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 1/3] drm/amd/display: Rework registers tracepoint Rodrigo Siqueira
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Rodrigo Siqueira @ 2020-09-09 22:53 UTC (permalink / raw)
To: amd-gfx, dri-devel, linux-kernel
Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König,
David Airlie, Daniel Vetter, Nicholas Kazlauskas, hersenxs.wu
Debug issues related to display can be a challenge due to the complexity
around this topic and different source of information might help in this
process. We already have support for tracepoints inside the display
component, i.e., we have the basic functionalities available and we just
need to expand it in order to make it more valuable for debugging. For
this reason, this patchset reworks part of the current tracepoint
options and add different sets of tracing inside amdgpu_dm, display
core, and DCN10. The first patch of this series just rework part of the
current tracepoints and the last set of patches introduces new
tracepoints.
This first patchset version is functional. Please, let me know what I
can improve in the current version but also let me know what kind of
tracepoint I can add for the next version.
Finally, I want to highlight that this work is based on a set of patches
originally made by Nicholas Kazlauskas.
Rodrigo Siqueira (3):
drm/amd/display: Rework registers tracepoint
drm/amd/display: Add tracepoint for amdgpu_dm
drm/amd/display: Add pipe_state tracepoint
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 514 ++++++++++++++++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +-
4 files changed, 523 insertions(+), 36 deletions(-)
--
2.28.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/3] drm/amd/display: Rework registers tracepoint
2020-09-09 22:53 [PATCH 0/3] Enlarge tracepoints in the display component Rodrigo Siqueira
@ 2020-09-09 22:53 ` Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 2/3] drm/amd/display: Add tracepoint for amdgpu_dm Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 3/3] drm/amd/display: Add pipe_state tracepoint Rodrigo Siqueira
2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Siqueira @ 2020-09-09 22:53 UTC (permalink / raw)
To: amd-gfx, dri-devel, linux-kernel
Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König,
David Airlie, Daniel Vetter, Nicholas Kazlauskas, hersenxs.wu
amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason,
this commits abstract these two events by using DECLARE_EVENT_CLASS and
create an instance of it for each one of these events.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 55 ++++++++-----------
1 file changed, 24 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index d898981684d5..dd34e11b1079 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -31,40 +31,33 @@
#include <linux/tracepoint.h>
-TRACE_EVENT(amdgpu_dc_rreg,
- TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value),
- TP_ARGS(read_count, reg, value),
- TP_STRUCT__entry(
- __field(uint32_t, reg)
- __field(uint32_t, value)
- ),
- TP_fast_assign(
- __entry->reg = reg;
- __entry->value = value;
- *read_count = *read_count + 1;
- ),
- TP_printk("reg=0x%08lx, value=0x%08lx",
- (unsigned long)__entry->reg,
- (unsigned long)__entry->value)
-);
+DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
+ TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+ TP_ARGS(count, reg, value),
-TRACE_EVENT(amdgpu_dc_wreg,
- TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value),
- TP_ARGS(write_count, reg, value),
- TP_STRUCT__entry(
- __field(uint32_t, reg)
- __field(uint32_t, value)
- ),
- TP_fast_assign(
- __entry->reg = reg;
- __entry->value = value;
- *write_count = *write_count + 1;
- ),
- TP_printk("reg=0x%08lx, value=0x%08lx",
- (unsigned long)__entry->reg,
- (unsigned long)__entry->value)
+ TP_STRUCT__entry(
+ __field(uint32_t, reg)
+ __field(uint32_t, value)
+ ),
+
+ TP_fast_assign(
+ __entry->reg = reg;
+ __entry->value = value;
+ *count = *count + 1;
+ ),
+
+ TP_printk("reg=0x%08lx, value=0x%08lx",
+ (unsigned long)__entry->reg,
+ (unsigned long)__entry->value)
);
+DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
+ TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+ TP_ARGS(count, reg, value));
+
+DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
+ TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+ TP_ARGS(count, reg, value));
TRACE_EVENT(amdgpu_dc_performance,
TP_PROTO(unsigned long read_count, unsigned long write_count,
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amd/display: Add tracepoint for amdgpu_dm
2020-09-09 22:53 [PATCH 0/3] Enlarge tracepoints in the display component Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 1/3] drm/amd/display: Rework registers tracepoint Rodrigo Siqueira
@ 2020-09-09 22:53 ` Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 3/3] drm/amd/display: Add pipe_state tracepoint Rodrigo Siqueira
2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Siqueira @ 2020-09-09 22:53 UTC (permalink / raw)
To: amd-gfx, dri-devel, linux-kernel
Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König,
David Airlie, Daniel Vetter, Nicholas Kazlauskas, hersenxs.wu
Debug amdgpu_dm could be a complicated task, therefore, this commit adds
tracepoints in some convenient functions such as plane and connector
check inside amdgpu_dm.
Co-developed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 ++
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 287 ++++++++++++++++++
2 files changed, 304 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cb624ee70545..552ca67c2a71 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5424,6 +5424,8 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
struct drm_crtc_state *new_crtc_state;
int ret;
+ trace_amdgpu_dm_connector_atomic_check(new_con_state);
+
if (!crtc)
return 0;
@@ -5542,6 +5544,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
int ret = -EINVAL;
+ trace_amdgpu_dm_crtc_atomic_check(state);
+
dm_update_crtc_active_planes(crtc, state);
if (unlikely(!dm_crtc_state->stream &&
@@ -5916,6 +5920,8 @@ static int dm_plane_atomic_check(struct drm_plane *plane,
struct drm_crtc_state *new_crtc_state;
int ret;
+ trace_amdgpu_dm_plane_atomic_check(state);
+
dm_plane_state = to_dm_plane_state(state);
if (!dm_plane_state->dc_state)
@@ -5956,6 +5962,8 @@ static void dm_plane_atomic_async_update(struct drm_plane *plane,
struct drm_plane_state *old_state =
drm_atomic_get_old_plane_state(new_state->state, plane);
+ trace_amdgpu_dm_atomic_update_cursor(new_state);
+
swap(plane->state->fb, new_state->fb);
plane->state->src_x = new_state->src_x;
@@ -7546,6 +7554,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
int crtc_disable_count = 0;
bool mode_set_reset_required = false;
+ trace_amdgpu_dm_atomic_commit_tail_begin(state);
+
drm_atomic_helper_update_legacy_modeset_state(dev, state);
dm_state = dm_atomic_get_new_state(state);
@@ -8616,6 +8626,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
int ret, i;
bool lock_and_validation_needed = false;
+ trace_amdgpu_dm_atomic_check_begin(state);
+
ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
goto fail;
@@ -8912,6 +8924,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
/* Must be success */
WARN_ON(ret);
+
+ trace_amdgpu_dm_atomic_check_finish(state, ret);
+
return ret;
fail:
@@ -8922,6 +8937,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
else
DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
+ trace_amdgpu_dm_atomic_check_finish(state, ret);
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index dd34e11b1079..5fb4c4a5c349 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -30,6 +30,12 @@
#define _AMDGPU_DM_TRACE_H_
#include <linux/tracepoint.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_atomic.h>
DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
@@ -89,6 +95,287 @@ TRACE_EVENT(amdgpu_dc_performance,
(unsigned long)__entry->write_delta,
(unsigned long)__entry->writes)
);
+
+TRACE_EVENT(amdgpu_dm_connector_atomic_check,
+ TP_PROTO(const struct drm_connector_state *state),
+ TP_ARGS(state),
+
+ TP_STRUCT__entry(
+ __field(uint32_t, conn_id)
+ __field(const struct drm_connector_state *, conn_state)
+ __field(const struct drm_atomic_state *, state)
+ __field(const struct drm_crtc_commit *, commit)
+ __field(uint32_t, crtc_id)
+ __field(uint32_t, best_encoder_id)
+ __field(enum drm_link_status, link_status)
+ __field(bool, self_refresh_aware)
+ __field(enum hdmi_picture_aspect, picture_aspect_ratio)
+ __field(unsigned int, content_type)
+ __field(unsigned int, hdcp_content_type)
+ __field(unsigned int, content_protection)
+ __field(unsigned int, scaling_mode)
+ __field(u32, colorspace)
+ __field(u8, max_requested_bpc)
+ __field(u8, max_bpc)
+ ),
+
+ TP_fast_assign(
+ __entry->conn_id = state->connector->base.id;
+ __entry->conn_state = state;
+ __entry->state = state->state;
+ __entry->commit = state->commit;
+ __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
+ __entry->best_encoder_id = state->best_encoder ?
+ state->best_encoder->base.id : 0;
+ __entry->link_status = state->link_status;
+ __entry->self_refresh_aware = state->self_refresh_aware;
+ __entry->picture_aspect_ratio = state->picture_aspect_ratio;
+ __entry->content_type = state->content_type;
+ __entry->hdcp_content_type = state->hdcp_content_type;
+ __entry->content_protection = state->content_protection;
+ __entry->scaling_mode = state->scaling_mode;
+ __entry->colorspace = state->colorspace;
+ __entry->max_requested_bpc = state->max_requested_bpc;
+ __entry->max_bpc = state->max_bpc;
+ ),
+
+ TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "
+ "best_encoder_id=%u link_status=%d self_refresh_aware=%d "
+ "picture_aspect_ratio=%d content_type=%u "
+ "hdcp_content_type=%u content_protection=%u scaling_mode=%u "
+ "colorspace=%u max_requested_bpc=%u max_bpc=%u",
+ __entry->conn_id, __entry->conn_state, __entry->state,
+ __entry->commit, __entry->crtc_id, __entry->best_encoder_id,
+ __entry->link_status, __entry->self_refresh_aware,
+ __entry->picture_aspect_ratio, __entry->content_type,
+ __entry->hdcp_content_type, __entry->content_protection,
+ __entry->scaling_mode, __entry->colorspace,
+ __entry->max_requested_bpc, __entry->max_bpc)
+);
+
+TRACE_EVENT(amdgpu_dm_crtc_atomic_check,
+ TP_PROTO(const struct drm_crtc_state *state),
+ TP_ARGS(state),
+
+ TP_STRUCT__entry(
+ __field(const struct drm_atomic_state *, state)
+ __field(const struct drm_crtc_state *, crtc_state)
+ __field(const struct drm_crtc_commit *, commit)
+ __field(uint32_t, crtc_id)
+ __field(bool, enable)
+ __field(bool, active)
+ __field(bool, planes_changed)
+ __field(bool, mode_changed)
+ __field(bool, active_changed)
+ __field(bool, connectors_changed)
+ __field(bool, zpos_changed)
+ __field(bool, color_mgmt_changed)
+ __field(bool, no_vblank)
+ __field(bool, async_flip)
+ __field(bool, vrr_enabled)
+ __field(bool, self_refresh_active)
+ __field(u32, plane_mask)
+ __field(u32, connector_mask)
+ __field(u32, encoder_mask)
+ ),
+
+ TP_fast_assign(
+ __entry->state = state->state;
+ __entry->crtc_state = state;
+ __entry->crtc_id = state->crtc->base.id;
+ __entry->commit = state->commit;
+ __entry->enable = state->enable;
+ __entry->active = state->active;
+ __entry->planes_changed = state->planes_changed;
+ __entry->mode_changed = state->mode_changed;
+ __entry->active_changed = state->active_changed;
+ __entry->connectors_changed = state->connectors_changed;
+ __entry->zpos_changed = state->zpos_changed;
+ __entry->color_mgmt_changed = state->color_mgmt_changed;
+ __entry->no_vblank = state->no_vblank;
+ __entry->async_flip = state->async_flip;
+ __entry->vrr_enabled = state->vrr_enabled;
+ __entry->self_refresh_active = state->self_refresh_active;
+ __entry->plane_mask = state->plane_mask;
+ __entry->connector_mask = state->connector_mask;
+ __entry->encoder_mask = state->encoder_mask;
+ ),
+
+ TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("
+ "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "
+ "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "
+ "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "
+ "enc=%x)",
+ __entry->crtc_id, __entry->crtc_state, __entry->state,
+ __entry->commit, __entry->planes_changed,
+ __entry->mode_changed, __entry->active_changed,
+ __entry->connectors_changed, __entry->zpos_changed,
+ __entry->color_mgmt_changed, __entry->enable, __entry->active,
+ __entry->async_flip, __entry->vrr_enabled,
+ __entry->self_refresh_active, __entry->no_vblank,
+ __entry->plane_mask, __entry->connector_mask,
+ __entry->encoder_mask)
+);
+
+DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,
+ TP_PROTO(const struct drm_plane_state *state),
+ TP_ARGS(state),
+ TP_STRUCT__entry(
+ __field(uint32_t, plane_id)
+ __field(enum drm_plane_type, plane_type)
+ __field(const struct drm_plane_state *, plane_state)
+ __field(const struct drm_atomic_state *, state)
+ __field(uint32_t, crtc_id)
+ __field(uint32_t, fb_id)
+ __field(uint32_t, fb_format)
+ __field(uint8_t, fb_planes)
+ __field(uint64_t, fb_modifier)
+ __field(const struct dma_fence *, fence)
+ __field(int32_t, crtc_x)
+ __field(int32_t, crtc_y)
+ __field(uint32_t, crtc_w)
+ __field(uint32_t, crtc_h)
+ __field(uint32_t, src_x)
+ __field(uint32_t, src_y)
+ __field(uint32_t, src_w)
+ __field(uint32_t, src_h)
+ __field(u32, alpha)
+ __field(uint32_t, pixel_blend_mode)
+ __field(unsigned int, rotation)
+ __field(unsigned int, zpos)
+ __field(unsigned int, normalized_zpos)
+ __field(enum drm_color_encoding, color_encoding)
+ __field(enum drm_color_range, color_range)
+ __field(bool, visible)
+ ),
+
+ TP_fast_assign(
+ __entry->plane_id = state->plane->base.id;
+ __entry->plane_type = state->plane->type;
+ __entry->plane_state = state;
+ __entry->state = state->state;
+ __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
+ __entry->fb_id = state->fb ? state->fb->base.id : 0;
+ __entry->fb_format = state->fb ? state->fb->format->format : 0;
+ __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;
+ __entry->fb_modifier = state->fb ? state->fb->modifier : 0;
+ __entry->fence = state->fence;
+ __entry->crtc_x = state->crtc_x;
+ __entry->crtc_y = state->crtc_y;
+ __entry->crtc_w = state->crtc_w;
+ __entry->crtc_h = state->crtc_h;
+ __entry->src_x = state->src_x >> 16;
+ __entry->src_y = state->src_y >> 16;
+ __entry->src_w = state->src_w >> 16;
+ __entry->src_h = state->src_h >> 16;
+ __entry->alpha = state->alpha;
+ __entry->pixel_blend_mode = state->pixel_blend_mode;
+ __entry->rotation = state->rotation;
+ __entry->zpos = state->zpos;
+ __entry->normalized_zpos = state->normalized_zpos;
+ __entry->color_encoding = state->color_encoding;
+ __entry->color_range = state->color_range;
+ __entry->visible = state->visible;
+ ),
+
+ TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "
+ "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "
+ "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "
+ "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "
+ "pixel_blend_mode=%u rotation=%u zpos=%u "
+ "normalized_zpos=%u color_encoding=%d color_range=%d "
+ "visible=%d",
+ __entry->plane_id, __entry->plane_type, __entry->plane_state,
+ __entry->state, __entry->crtc_id, __entry->fb_id,
+ (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',
+ ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',
+ ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',
+ ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',
+ __entry->fb_planes,
+ __entry->fb_modifier, __entry->fence, __entry->crtc_x,
+ __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
+ __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,
+ __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,
+ __entry->zpos, __entry->normalized_zpos,
+ __entry->color_encoding, __entry->color_range,
+ __entry->visible)
+);
+
+DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,
+ TP_PROTO(const struct drm_plane_state *state),
+ TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,
+ TP_PROTO(const struct drm_plane_state *state),
+ TP_ARGS(state));
+
+TRACE_EVENT(amdgpu_dm_atomic_state_template,
+ TP_PROTO(const struct drm_atomic_state *state),
+ TP_ARGS(state),
+
+ TP_STRUCT__entry(
+ __field(const struct drm_atomic_state *, state)
+ __field(bool, allow_modeset)
+ __field(bool, legacy_cursor_update)
+ __field(bool, async_update)
+ __field(bool, duplicated)
+ __field(int, num_connector)
+ __field(int, num_private_objs)
+ ),
+
+ TP_fast_assign(
+ __entry->state = state;
+ __entry->allow_modeset = state->allow_modeset;
+ __entry->legacy_cursor_update = state->legacy_cursor_update;
+ __entry->async_update = state->async_update;
+ __entry->duplicated = state->duplicated;
+ __entry->num_connector = state->num_connector;
+ __entry->num_private_objs = state->num_private_objs;
+ ),
+
+ TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "
+ "async_update=%d duplicated=%d num_connector=%d "
+ "num_private_objs=%d",
+ __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,
+ __entry->async_update, __entry->duplicated, __entry->num_connector,
+ __entry->num_private_objs)
+);
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,
+ TP_PROTO(const struct drm_atomic_state *state),
+ TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,
+ TP_PROTO(const struct drm_atomic_state *state),
+ TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,
+ TP_PROTO(const struct drm_atomic_state *state),
+ TP_ARGS(state));
+
+TRACE_EVENT(amdgpu_dm_atomic_check_finish,
+ TP_PROTO(const struct drm_atomic_state *state, int res),
+ TP_ARGS(state, res),
+
+ TP_STRUCT__entry(
+ __field(const struct drm_atomic_state *, state)
+ __field(int, res)
+ __field(bool, async_update)
+ __field(bool, allow_modeset)
+ ),
+
+ TP_fast_assign(
+ __entry->state = state;
+ __entry->res = res;
+ __entry->async_update = state->async_update;
+ __entry->allow_modeset = state->allow_modeset;
+ ),
+
+ TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",
+ __entry->state, __entry->res,
+ __entry->async_update, __entry->allow_modeset)
+);
+
#endif /* _AMDGPU_DM_TRACE_H_ */
#undef TRACE_INCLUDE_PATH
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amd/display: Add pipe_state tracepoint
2020-09-09 22:53 [PATCH 0/3] Enlarge tracepoints in the display component Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 1/3] drm/amd/display: Rework registers tracepoint Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 2/3] drm/amd/display: Add tracepoint for amdgpu_dm Rodrigo Siqueira
@ 2020-09-09 22:53 ` Rodrigo Siqueira
2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Siqueira @ 2020-09-09 22:53 UTC (permalink / raw)
To: amd-gfx, dri-devel, linux-kernel
Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König,
David Airlie, Daniel Vetter, Nicholas Kazlauskas, hersenxs.wu
This commit introduces a trace mechanism for struct pipe_ctx by adding a
middle layer struct in the amdgpu_dm_trace.h for capturing the most
important data from struct pipe_ctx and showing its data via tracepoint.
This tracepoint was added to dc.c and dcn10_hw_sequencer, however, it
can be added to other DCN architecture.
Co-developed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 172 ++++++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +-
3 files changed, 195 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index 5fb4c4a5c349..53f62506e17c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -376,6 +376,178 @@ TRACE_EVENT(amdgpu_dm_atomic_check_finish,
__entry->async_update, __entry->allow_modeset)
);
+#ifndef _AMDGPU_DM_TRACE_STRUCTS_DEFINED_
+#define _AMDGPU_DM_TRACE_STRUCTS_DEFINED_
+
+struct amdgpu_dm_trace_pipe_state {
+ int pipe_idx;
+ const void *stream;
+ int stream_w;
+ int stream_h;
+ int dst_x;
+ int dst_y;
+ int dst_w;
+ int dst_h;
+ int src_x;
+ int src_y;
+ int src_w;
+ int src_h;
+ int clip_x;
+ int clip_y;
+ int clip_w;
+ int clip_h;
+ int recout_x;
+ int recout_y;
+ int recout_w;
+ int recout_h;
+ int viewport_x;
+ int viewport_y;
+ int viewport_w;
+ int viewport_h;
+ int flip_immediate;
+ int surface_pitch;
+ int format;
+ int swizzle;
+ unsigned int update_flags;
+};
+
+#define fill_out_trace_pipe_state(trace_pipe_state, pipe_ctx) \
+ do { \
+ trace_pipe_state.pipe_idx = (pipe_ctx)->pipe_idx; \
+ trace_pipe_state.stream = (pipe_ctx)->stream; \
+ trace_pipe_state.stream_w = (pipe_ctx)->stream->timing.h_addressable; \
+ trace_pipe_state.stream_h = (pipe_ctx)->stream->timing.v_addressable; \
+ trace_pipe_state.dst_x = (pipe_ctx)->plane_state->dst_rect.x; \
+ trace_pipe_state.dst_y = (pipe_ctx)->plane_state->dst_rect.y; \
+ trace_pipe_state.dst_w = (pipe_ctx)->plane_state->dst_rect.width; \
+ trace_pipe_state.dst_h = (pipe_ctx)->plane_state->dst_rect.height; \
+ trace_pipe_state.src_x = (pipe_ctx)->plane_state->src_rect.x; \
+ trace_pipe_state.src_y = (pipe_ctx)->plane_state->src_rect.y; \
+ trace_pipe_state.src_w = (pipe_ctx)->plane_state->src_rect.width; \
+ trace_pipe_state.src_h = (pipe_ctx)->plane_state->src_rect.height; \
+ trace_pipe_state.clip_x = (pipe_ctx)->plane_state->clip_rect.x; \
+ trace_pipe_state.clip_y = (pipe_ctx)->plane_state->clip_rect.y; \
+ trace_pipe_state.clip_w = (pipe_ctx)->plane_state->clip_rect.width; \
+ trace_pipe_state.clip_h = (pipe_ctx)->plane_state->clip_rect.height; \
+ trace_pipe_state.recout_x = (pipe_ctx)->plane_res.scl_data.recout.x; \
+ trace_pipe_state.recout_y = (pipe_ctx)->plane_res.scl_data.recout.y; \
+ trace_pipe_state.recout_w = (pipe_ctx)->plane_res.scl_data.recout.width; \
+ trace_pipe_state.recout_h = (pipe_ctx)->plane_res.scl_data.recout.height; \
+ trace_pipe_state.viewport_x = (pipe_ctx)->plane_res.scl_data.viewport.x; \
+ trace_pipe_state.viewport_y = (pipe_ctx)->plane_res.scl_data.viewport.y; \
+ trace_pipe_state.viewport_w = (pipe_ctx)->plane_res.scl_data.viewport.width; \
+ trace_pipe_state.viewport_h = (pipe_ctx)->plane_res.scl_data.viewport.height; \
+ trace_pipe_state.flip_immediate = (pipe_ctx)->plane_state->flip_immediate; \
+ trace_pipe_state.surface_pitch = (pipe_ctx)->plane_state->plane_size.surface_pitch; \
+ trace_pipe_state.format = (pipe_ctx)->plane_state->format; \
+ trace_pipe_state.swizzle = (pipe_ctx)->plane_state->tiling_info.gfx9.swizzle; \
+ trace_pipe_state.update_flags = (pipe_ctx)->update_flags.raw; \
+ } while (0)
+
+#endif /* _AMDGPU_DM_TRACE_STRUCTS_DEFINED_ */
+
+TRACE_EVENT(amdgpu_dm_dc_pipe_state,
+ TP_PROTO(const struct amdgpu_dm_trace_pipe_state *pipe_state),
+ TP_ARGS(pipe_state),
+ TP_STRUCT__entry(
+ __field(int, pipe_idx)
+ __field(const void *, stream)
+ __field(int, stream_w)
+ __field(int, stream_h)
+ __field(int, dst_x)
+ __field(int, dst_y)
+ __field(int, dst_w)
+ __field(int, dst_h)
+ __field(int, src_x)
+ __field(int, src_y)
+ __field(int, src_w)
+ __field(int, src_h)
+ __field(int, clip_x)
+ __field(int, clip_y)
+ __field(int, clip_w)
+ __field(int, clip_h)
+ __field(int, recout_x)
+ __field(int, recout_y)
+ __field(int, recout_w)
+ __field(int, recout_h)
+ __field(int, viewport_x)
+ __field(int, viewport_y)
+ __field(int, viewport_w)
+ __field(int, viewport_h)
+ __field(int, flip_immediate)
+ __field(int, surface_pitch)
+ __field(int, format)
+ __field(int, swizzle)
+ __field(unsigned int, update_flags)
+ ),
+
+ TP_fast_assign(
+ __entry->pipe_idx = pipe_state->pipe_idx;
+ __entry->stream = pipe_state->stream;
+ __entry->stream_w = pipe_state->stream_w;
+ __entry->stream_h = pipe_state->stream_h;
+ __entry->dst_x = pipe_state->dst_x;
+ __entry->dst_y = pipe_state->dst_y;
+ __entry->dst_w = pipe_state->dst_w;
+ __entry->dst_h = pipe_state->dst_h;
+ __entry->src_x = pipe_state->src_x;
+ __entry->src_y = pipe_state->src_y;
+ __entry->src_w = pipe_state->src_w;
+ __entry->src_h = pipe_state->src_h;
+ __entry->clip_x = pipe_state->clip_x;
+ __entry->clip_y = pipe_state->clip_y;
+ __entry->clip_w = pipe_state->clip_w;
+ __entry->clip_h = pipe_state->clip_h;
+ __entry->recout_x = pipe_state->recout_x;
+ __entry->recout_y = pipe_state->recout_y;
+ __entry->recout_w = pipe_state->recout_w;
+ __entry->recout_h = pipe_state->recout_h;
+ __entry->viewport_x = pipe_state->viewport_x;
+ __entry->viewport_y = pipe_state->viewport_y;
+ __entry->viewport_w = pipe_state->viewport_w;
+ __entry->viewport_h = pipe_state->viewport_h;
+ __entry->flip_immediate = pipe_state->flip_immediate;
+ __entry->surface_pitch = pipe_state->surface_pitch;
+ __entry->format = pipe_state->format;
+ __entry->swizzle = pipe_state->swizzle;
+ __entry->update_flags = pipe_state->update_flags;
+ ),
+ TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "
+ "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "
+ "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "
+ "format=%d swizzle=%d update_flags=%x",
+ __entry->pipe_idx,
+ __entry->stream,
+ __entry->stream_w,
+ __entry->stream_h,
+ __entry->dst_x,
+ __entry->dst_y,
+ __entry->dst_w,
+ __entry->dst_h,
+ __entry->src_x,
+ __entry->src_y,
+ __entry->src_w,
+ __entry->src_h,
+ __entry->clip_x,
+ __entry->clip_y,
+ __entry->clip_w,
+ __entry->clip_h,
+ __entry->recout_x,
+ __entry->recout_y,
+ __entry->recout_w,
+ __entry->recout_h,
+ __entry->viewport_x,
+ __entry->viewport_y,
+ __entry->viewport_w,
+ __entry->viewport_h,
+ __entry->flip_immediate,
+ __entry->surface_pitch,
+ __entry->format,
+ __entry->swizzle,
+ __entry->update_flags
+ )
+);
+
#endif /* _AMDGPU_DM_TRACE_H_ */
#undef TRACE_INCLUDE_PATH
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dc463d99ef50..0c9f177e5827 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2644,6 +2644,17 @@ void dc_commit_updates_for_stream(struct dc *dc,
}
}
+ for (i = 0; i < MAX_PIPES; ++i) {
+ struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->plane_state) {
+ struct amdgpu_dm_trace_pipe_state pipe_state_trace;
+
+ fill_out_trace_pipe_state(pipe_state_trace, pipe_ctx);
+ trace_amdgpu_dm_dc_pipe_state(&pipe_state_trace);
+ }
+ }
+
commit_planes_for_stream(
dc,
srf_updates,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8ca94f506195..464d0ad093b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1020,15 +1020,22 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
}
-
void dcn10_verify_allow_pstate_change_high(struct dc *dc)
{
- static bool should_log_hw_state; /* prevent hw state log by default */
-
if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
- if (should_log_hw_state) {
- dcn10_log_hw_state(dc, NULL);
+ int i;
+
+ for (i = 0; i < MAX_PIPES; ++i) {
+ struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->plane_state) {
+ struct amdgpu_dm_trace_pipe_state pipe_state_trace;
+
+ fill_out_trace_pipe_state(pipe_state_trace, pipe_ctx);
+ trace_amdgpu_dm_dc_pipe_state(&pipe_state_trace);
+ }
}
+
BREAK_TO_DEBUGGER();
if (dcn10_hw_wa_force_recovery(dc)) {
/*check again*/
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-10 3:25 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-09 22:53 [PATCH 0/3] Enlarge tracepoints in the display component Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 1/3] drm/amd/display: Rework registers tracepoint Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 2/3] drm/amd/display: Add tracepoint for amdgpu_dm Rodrigo Siqueira
2020-09-09 22:53 ` [PATCH 3/3] drm/amd/display: Add pipe_state tracepoint Rodrigo Siqueira
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