* [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC
@ 2020-09-14 15:21 Kishon Vijay Abraham I
2020-09-14 15:21 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Kishon Vijay Abraham I
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Kishon Vijay Abraham I @ 2020-09-14 15:21 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon, Rob Herring
Cc: linux-arm-kernel, devicetree, linux-kernel, Kishon Vijay Abraham I
Now that J721E PCIe support is merged (including the YAML bindings),
add PCIe device tree nodes to get PCIe working in J721E SoC both in
RC mode and EP mode.
Series has been rebased to:
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux ti-k3-dts-next
Changes from v1:
1) Renamed all syscon dt-nodes to "syscon" instead of pcieX-ctrl.
2) Add TI specific compatible for "syscon" DT nodes
3) Add information about appending "ranges" property to access all PCIe
instances in commit log.
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe
instances
.../dts/ti/k3-j721e-common-proc-board.dts | 80 ++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 232 +++++++++++++++++-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +-
3 files changed, 315 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes 2020-09-14 15:21 [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I @ 2020-09-14 15:21 ` Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances Kishon Vijay Abraham I ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2020-09-14 15:21 UTC (permalink / raw) To: Tero Kristo, Nishanth Menon, Rob Herring Cc: linux-arm-kernel, devicetree, linux-kernel, Kishon Vijay Abraham I Add PCIe device tree nodes (both RC and EP) for the four PCIe instances here. Also add the missing translations required in the "ranges" DT property of cbass_main to access all the four PCIe instances. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 232 +++++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- 2 files changed, 235 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 00a36a14efe7..c9045f005a62 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,7 +28,39 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + pcie0_ctrl: syscon@4070 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004070 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4070 0x4070 0x4>; + }; + + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + + pcie2_ctrl: syscon@4078 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004078 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4078 0x4078 0x4>; + }; + + pcie3_ctrl: syscon@407c { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0000407c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x407c 0x407c 0x4>; + }; + + serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; #mux-control-cells = <1>; @@ -576,6 +608,204 @@ }; }; + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie2_rc: pcie@2920000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x20000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie2_ep: pcie-ep@2920000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie3_ep: pcie-ep@2930000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + #address-cells = <2>; + #size-cells = <2>; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index f787aa73aaae..eeb02115b966 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -132,9 +132,12 @@ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances 2020-09-14 15:21 [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Kishon Vijay Abraham I @ 2020-09-14 15:21 ` Kishon Vijay Abraham I 2020-09-14 16:10 ` [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Nishanth Menon 2020-09-16 12:35 ` Nishanth Menon 3 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2020-09-14 15:21 UTC (permalink / raw) To: Tero Kristo, Nishanth Menon, Rob Herring Cc: linux-arm-kernel, devicetree, linux-kernel, Kishon Vijay Abraham I J721E Common Processor Board has PCIe connectors for the 1st three PCIe instances. Configure the three PCIe instances in RC mode and disable the 4th PCIe instance. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../dts/ti/k3-j721e-common-proc-board.dts | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c355692796a9..8b57d22ca3cc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -558,3 +558,83 @@ status = "okay"; }; + +&serdes0 { + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes2 { + serdes2_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie2_rc { + reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + +&pcie1_ep { + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie2_ep { + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie3_rc { + status = "disabled"; +}; + +&pcie3_ep { + status = "disabled"; +}; -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC 2020-09-14 15:21 [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances Kishon Vijay Abraham I @ 2020-09-14 16:10 ` Nishanth Menon 2020-09-15 12:40 ` Kishon Vijay Abraham I 2020-09-16 12:35 ` Nishanth Menon 3 siblings, 1 reply; 7+ messages in thread From: Nishanth Menon @ 2020-09-14 16:10 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 20:51-20200914, Kishon Vijay Abraham I wrote: > Now that J721E PCIe support is merged (including the YAML bindings), > add PCIe device tree nodes to get PCIe working in J721E SoC both in > RC mode and EP mode. > > Series has been rebased to: > git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux ti-k3-dts-next > > Changes from v1: > 1) Renamed all syscon dt-nodes to "syscon" instead of pcieX-ctrl. > 2) Add TI specific compatible for "syscon" DT nodes > 3) Add information about appending "ranges" property to access all PCIe > instances in commit log. > > Kishon Vijay Abraham I (2): > arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes > arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe > instances > > .../dts/ti/k3-j721e-common-proc-board.dts | 80 ++++++ > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 232 +++++++++++++++++- > arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- > 3 files changed, 315 insertions(+), 2 deletions(-) > > -- > 2.17.1 > Thanks, yeah - the series is clean. If no one adds a tag in the next couple of days or so, I can pick it up. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC 2020-09-14 16:10 ` [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Nishanth Menon @ 2020-09-15 12:40 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 7+ messages in thread From: Kishon Vijay Abraham I @ 2020-09-15 12:40 UTC (permalink / raw) To: Nishanth Menon Cc: Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 14/09/20 9:40 pm, Nishanth Menon wrote: > On 20:51-20200914, Kishon Vijay Abraham I wrote: >> Now that J721E PCIe support is merged (including the YAML bindings), >> add PCIe device tree nodes to get PCIe working in J721E SoC both in >> RC mode and EP mode. >> >> Series has been rebased to: >> git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux ti-k3-dts-next >> >> Changes from v1: >> 1) Renamed all syscon dt-nodes to "syscon" instead of pcieX-ctrl. >> 2) Add TI specific compatible for "syscon" DT nodes >> 3) Add information about appending "ranges" property to access all PCIe >> instances in commit log. >> >> Kishon Vijay Abraham I (2): >> arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes >> arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe >> instances >> >> .../dts/ti/k3-j721e-common-proc-board.dts | 80 ++++++ >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 232 +++++++++++++++++- >> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- >> 3 files changed, 315 insertions(+), 2 deletions(-) >> >> -- >> 2.17.1 >> > > Thanks, yeah - the series is clean. If no one adds a tag in the next > couple of days or so, I can pick it up. > Thanks Nishanth! Regards Kishon ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC 2020-09-14 15:21 [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I ` (2 preceding siblings ...) 2020-09-14 16:10 ` [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Nishanth Menon @ 2020-09-16 12:35 ` Nishanth Menon 2020-09-16 12:35 ` Nishanth Menon 3 siblings, 1 reply; 7+ messages in thread From: Nishanth Menon @ 2020-09-16 12:35 UTC (permalink / raw) To: Rob Herring, Kishon Vijay Abraham I, Tero Kristo Cc: Nishanth Menon, linux-kernel, devicetree, linux-arm-kernel ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC 2020-09-16 12:35 ` Nishanth Menon @ 2020-09-16 12:35 ` Nishanth Menon 0 siblings, 0 replies; 7+ messages in thread From: Nishanth Menon @ 2020-09-16 12:35 UTC (permalink / raw) To: Rob Herring, Kishon Vijay Abraham I, Tero Kristo Cc: Nishanth Menon, linux-kernel, devicetree, linux-arm-kernel On Mon, 14 Sep 2020 20:51:13 +0530, Kishon Vijay Abraham I wrote: > Now that J721E PCIe support is merged (including the YAML bindings), > add PCIe device tree nodes to get PCIe working in J721E SoC both in > RC mode and EP mode. > > Series has been rebased to: > git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux ti-k3-dts-next > > [...] Hi Kishon Vijay Abraham I, I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes commit: 1a0361c153c2b241d9286d977ae6405a84efb4e4 [2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances commit: c5e91b849c807949959045a2fc03754404a74faa All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-09-17 11:10 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-09-14 15:21 [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Kishon Vijay Abraham I 2020-09-14 15:21 ` [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances Kishon Vijay Abraham I 2020-09-14 16:10 ` [PATCH v2 0/2] Add DT to get PCIe working in J721E SoC Nishanth Menon 2020-09-15 12:40 ` Kishon Vijay Abraham I 2020-09-16 12:35 ` Nishanth Menon 2020-09-16 12:35 ` Nishanth Menon
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