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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Vinod Koul <vkoul@kernel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	agross@kernel.org, kishon@ti.com, robh@kernel.org,
	svarbanov@mm-sol.com, bhelgaas@google.com,
	lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	mgautam@codeaurora.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 1/5] dt-bindings: phy: qcom,qmp: Document SM8250 PCIe PHY bindings
Date: Thu, 17 Sep 2020 00:10:08 -0500	[thread overview]
Message-ID: <20200917051008.GM1893@yoga> (raw)
In-Reply-To: <20200917043239.GW2968@vkoul-mobl>

On Wed 16 Sep 23:32 CDT 2020, Vinod Koul wrote:

> On 16-09-20, 17:45, Bjorn Andersson wrote:
> > On Wed 16 Sep 08:19 CDT 2020, Manivannan Sadhasivam wrote:
> > 
> > > Document the DT bindings of below PCIe PHY versions used on SM8250:
> > > 
> > > QMP GEN3x1 PHY - 1 lane
> > > QMP GEN3x2 PHY - 2 lanes
> > > QMP Modem PHY - 2 lanes
> > 
> > How about something like "Add the three PCIe PHYs found in SM8250 to the
> > QMP binding"?
> 
> Or add just one compatible sm8250-qmp-pcie and then use number of lanes
> as dt property?
> 

If we have the same initialization sequence then that sounds reasonable.
Perhaps we can derive the number of lanes from the child node?

A bigger question is how we deal with this going forward, if there are
more crazy setups like on sc8180x where the lanes might be grouped
differently based on board...

Regards,
Bjorn

> > 
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> > > index 185cdea9cf81..69b67f79075c 100644
> > > --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> > > @@ -31,6 +31,9 @@ properties:
> > >        - qcom,sdm845-qmp-usb3-uni-phy
> > >        - qcom,sm8150-qmp-ufs-phy
> > >        - qcom,sm8250-qmp-ufs-phy
> > > +      - qcom,qcom,sm8250-qmp-gen3x1-pcie-phy
> > > +      - qcom,qcom,sm8250-qmp-gen3x2-pcie-phy
> > > +      - qcom,qcom,sm8250-qmp-modem-pcie-phy
> > 
> > One "qcom," should be enough.
> > 
> > >  
> > >    reg:
> > >      items:
> > > @@ -259,6 +262,8 @@ allOf:
> > >              enum:
> > >                - qcom,sdm845-qhp-pcie-phy
> > >                - qcom,sdm845-qmp-pcie-phy
> > > +              - qcom,sm8250-qhp-pcie-phy
> > > +              - qcom,sm8250-qmp-pcie-phy
> > 
> > Adjust these.
> > 
> > Regards,
> > Bjorn
> > 
> > >      then:
> > >        properties:
> > >          clocks:
> > > -- 
> > > 2.17.1
> > > 
> 
> -- 
> ~Vinod

  reply	other threads:[~2020-09-17  5:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-16 13:19 [PATCH 0/5] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 13:19 ` [PATCH 1/5] dt-bindings: phy: qcom,qmp: Document SM8250 PCIe PHY bindings Manivannan Sadhasivam
2020-09-16 22:45   ` Bjorn Andersson
2020-09-17  4:32     ` Vinod Koul
2020-09-17  5:10       ` Bjorn Andersson [this message]
2020-09-16 13:19 ` [PATCH 2/5] phy: qualcomm: phy-qcom-qmp: Add PCIe PHY support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 22:53   ` Bjorn Andersson
2020-09-17  4:49   ` Vinod Koul
2020-09-16 13:19 ` [PATCH 3/5] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
2020-09-16 22:55   ` Bjorn Andersson
2020-09-16 13:19 ` [PATCH 4/5] pci: controller: dwc: qcom: Add PCIe support " Manivannan Sadhasivam
2020-09-16 22:04   ` Bjorn Helgaas
2020-09-23 15:58   ` Rob Herring
2020-09-16 13:20 ` [PATCH 5/5] pci: controller: dwc: qcom: Harcode PCIe config SID Manivannan Sadhasivam
2020-09-16 22:06   ` Bjorn Helgaas
2020-09-17  0:39   ` Bjorn Andersson

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