From: Rob Herring <robh@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
vkoul@kernel.org, svarbanov@mm-sol.com, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
mgautam@codeaurora.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 4/5] pci: controller: dwc: qcom: Add PCIe support for SM8250 SoC
Date: Wed, 23 Sep 2020 09:58:17 -0600 [thread overview]
Message-ID: <20200923155817.GA811543@bogus> (raw)
In-Reply-To: <20200916132000.1850-5-manivannan.sadhasivam@linaro.org>
On Wed, Sep 16, 2020 at 06:49:59PM +0530, Manivannan Sadhasivam wrote:
> The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence
> the support is added reusing the 2.7.0 ops. Only difference is the need
> of ATU base, which will be fetched opionally if provided by DT/ACPI.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 3aac77a295ba..ca8ad354e09d 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1370,6 +1370,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> struct pcie_port *pp;
> struct dw_pcie *pci;
> struct qcom_pcie *pcie;
> + void __iomem *atu_base;
> int ret;
>
> pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> @@ -1422,6 +1423,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> + /* Get the optional ATU region if provided */
> + atu_base = devm_platform_ioremap_resource_byname(pdev, "atu");
> + if (!IS_ERR(atu_base))
> + pci->atu_base = atu_base;
> +
This is getting moved to the DWC common code[1].
Rob
[1] https://lore.kernel.org/r/1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com
> pcie->phy = devm_phy_optional_get(dev, "pciephy");
> if (IS_ERR(pcie->phy)) {
> ret = PTR_ERR(pcie->phy);
> @@ -1476,6 +1482,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
> { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
> { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
> + { .compatible = "qcom,pcie-sm8250", .data = &ops_2_7_0 },
> { }
> };
>
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-09-23 15:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 13:19 [PATCH 0/5] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 13:19 ` [PATCH 1/5] dt-bindings: phy: qcom,qmp: Document SM8250 PCIe PHY bindings Manivannan Sadhasivam
2020-09-16 22:45 ` Bjorn Andersson
2020-09-17 4:32 ` Vinod Koul
2020-09-17 5:10 ` Bjorn Andersson
2020-09-16 13:19 ` [PATCH 2/5] phy: qualcomm: phy-qcom-qmp: Add PCIe PHY support for SM8250 SoC Manivannan Sadhasivam
2020-09-16 22:53 ` Bjorn Andersson
2020-09-17 4:49 ` Vinod Koul
2020-09-16 13:19 ` [PATCH 3/5] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
2020-09-16 22:55 ` Bjorn Andersson
2020-09-16 13:19 ` [PATCH 4/5] pci: controller: dwc: qcom: Add PCIe support " Manivannan Sadhasivam
2020-09-16 22:04 ` Bjorn Helgaas
2020-09-23 15:58 ` Rob Herring [this message]
2020-09-16 13:20 ` [PATCH 5/5] pci: controller: dwc: qcom: Harcode PCIe config SID Manivannan Sadhasivam
2020-09-16 22:06 ` Bjorn Helgaas
2020-09-17 0:39 ` Bjorn Andersson
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