[PATCH 0/1] Add CPU nodes for Ingenic SoCs.

[PATCH 0/1] Add CPU nodes for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files. This will be
used in the SMP driver later.

周琰杰 (Zhou Yanjie) (1):
  MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

 arch/mips/boot/dts/ingenic/jz4725b.dtsi | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/jz4740.dtsi  | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/jz4770.dtsi  | 15 ++++++++++++++-
 arch/mips/boot/dts/ingenic/jz4780.dtsi  | 23 +++++++++++++++++++++++
 arch/mips/boot/dts/ingenic/x1000.dtsi   | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi   | 14 ++++++++++++++
 6 files changed, 93 insertions(+), 1 deletion(-)

-- 
2.11.0

[PATCH 1/1] MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
 arch/mips/boot/dts/ingenic/jz4725b.dtsi | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/jz4740.dtsi  | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/jz4770.dtsi  | 15 ++++++++++++++-
 arch/mips/boot/dts/ingenic/jz4780.dtsi  | 23 +++++++++++++++++++++++
 arch/mips/boot/dts/ingenic/x1000.dtsi   | 14 ++++++++++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi   | 14 ++++++++++++++
 6 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
index a8fca560878d..a1f0b71c9223 100644
--- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
@@ -7,6 +7,20 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4725b";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-mxu1.0";
+			reg = <0>;
+
+			clocks = <&cgu JZ4725B_CLK_CCLK>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 1520585c235c..eee523678ce5 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -7,6 +7,20 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4740";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-mxu1.0";
+			reg = <0>;
+
+			clocks = <&cgu JZ4740_CLK_CCLK>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index fa11ac950499..018721a9eea9 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -1,5 +1,4 @@
 // SPDX-License-Identifier: GPL-2.0
-
 #include <dt-bindings/clock/jz4770-cgu.h>
 #include <dt-bindings/clock/ingenic,tcu.h>
 
@@ -8,6 +7,20 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4770";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+			reg = <0>;
+
+			clocks = <&cgu JZ4770_CLK_CCLK>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b7f409a7cf5d..dfb5a7e1bb21 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -8,6 +8,29 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4780";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+			reg = <0>;
+
+			clocks = <&cgu JZ4780_CLK_CPU>;
+			clock-names = "cpu";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+			reg = <1>;
+
+			clocks = <&cgu JZ4780_CLK_CORE1>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 9de9e7c2d523..1f1f896dd1f7 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -8,6 +8,20 @@
 	#size-cells = <1>;
 	compatible = "ingenic,x1000", "ingenic,x1000e";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+			reg = <0>;
+
+			clocks = <&cgu X1000_CLK_CPU>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index eb1214481a33..b05dac3ae308 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -8,6 +8,20 @@
 	#size-cells = <1>;
 	compatible = "ingenic,x1830";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "ingenic,xburst-fpu2.0-mxu2.0";
+			reg = <0>;
+
+			clocks = <&cgu X1830_CLK_CPU>;
+			clock-names = "cpu";
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
-- 
2.11.0

Re: [PATCH 1/1] MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

[Paul Cercueil]

Le sam. 19 sept. 2020 à 19:38, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
> jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.
> 
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Reviewed-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
>  arch/mips/boot/dts/ingenic/jz4725b.dtsi | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/jz4740.dtsi  | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/jz4770.dtsi  | 15 ++++++++++++++-
>  arch/mips/boot/dts/ingenic/jz4780.dtsi  | 23 +++++++++++++++++++++++
>  arch/mips/boot/dts/ingenic/x1000.dtsi   | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/x1830.dtsi   | 14 ++++++++++++++
>  6 files changed, 93 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
> index a8fca560878d..a1f0b71c9223 100644
> --- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
> @@ -7,6 +7,20 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,jz4725b";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-mxu1.0";
> +			reg = <0>;
> +
> +			clocks = <&cgu JZ4725B_CLK_CCLK>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4740.dtsi
> index 1520585c235c..eee523678ce5 100644
> --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
> @@ -7,6 +7,20 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,jz4740";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-mxu1.0";
> +			reg = <0>;
> +
> +			clocks = <&cgu JZ4740_CLK_CCLK>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> index fa11ac950499..018721a9eea9 100644
> --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> @@ -1,5 +1,4 @@
>  // SPDX-License-Identifier: GPL-2.0
> -
>  #include <dt-bindings/clock/jz4770-cgu.h>
>  #include <dt-bindings/clock/ingenic,tcu.h>
> 
> @@ -8,6 +7,20 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,jz4770";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> +			reg = <0>;
> +
> +			clocks = <&cgu JZ4770_CLK_CCLK>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi 
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index b7f409a7cf5d..dfb5a7e1bb21 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -8,6 +8,29 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,jz4780";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> +			reg = <0>;
> +
> +			clocks = <&cgu JZ4780_CLK_CPU>;
> +			clock-names = "cpu";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> +			reg = <1>;
> +
> +			clocks = <&cgu JZ4780_CLK_CORE1>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index 9de9e7c2d523..1f1f896dd1f7 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -8,6 +8,20 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,x1000", "ingenic,x1000e";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> +			reg = <0>;
> +
> +			clocks = <&cgu X1000_CLK_CPU>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi 
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index eb1214481a33..b05dac3ae308 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -8,6 +8,20 @@
>  	#size-cells = <1>;
>  	compatible = "ingenic,x1830";
> 
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "ingenic,xburst-fpu2.0-mxu2.0";
> +			reg = <0>;
> +
> +			clocks = <&cgu X1830_CLK_CPU>;
> +			clock-names = "cpu";
> +		};
> +	};
> +
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> --
> 2.11.0
> 

Re: [PATCH 1/1] MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

[Thomas Bogendoerfer]

On Sat, Sep 19, 2020 at 07:38:59PM +0800, 周琰杰 (Zhou Yanjie) wrote:
> Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
> jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.
> 
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
>  arch/mips/boot/dts/ingenic/jz4725b.dtsi | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/jz4740.dtsi  | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/jz4770.dtsi  | 15 ++++++++++++++-
>  arch/mips/boot/dts/ingenic/jz4780.dtsi  | 23 +++++++++++++++++++++++
>  arch/mips/boot/dts/ingenic/x1000.dtsi   | 14 ++++++++++++++
>  arch/mips/boot/dts/ingenic/x1830.dtsi   | 14 ++++++++++++++
>  6 files changed, 93 insertions(+), 1 deletion(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]