* [PATCH] arm64: tegra186: Add missing CPU PMUs
@ 2020-10-13 9:58 Marc Zyngier
2020-11-10 17:36 ` Thierry Reding
0 siblings, 1 reply; 5+ messages in thread
From: Marc Zyngier @ 2020-10-13 9:58 UTC (permalink / raw)
To: linux-tegra, linux-kernel
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Nagarjuna Kristam,
Sowjanya Komatineni, devicetree
Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++-----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index fd44545e124d..6bb03668a8d3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1321,7 +1321,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ denver_0: cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
@@ -1334,7 +1334,7 @@ cpu@0 {
reg = <0x000>;
};
- cpu@1 {
+ denver_1: cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
@@ -1347,7 +1347,7 @@ cpu@1 {
reg = <0x001>;
};
- cpu@2 {
+ ca57_0: cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1360,7 +1360,7 @@ cpu@2 {
reg = <0x100>;
};
- cpu@3 {
+ ca57_1: cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1373,7 +1373,7 @@ cpu@3 {
reg = <0x101>;
};
- cpu@4 {
+ ca57_2: cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1386,7 +1386,7 @@ cpu@4 {
reg = <0x102>;
};
- cpu@5 {
+ ca57_3: cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1418,6 +1418,22 @@ L2_A57: l2-cache1 {
};
};
+ pmu_denver {
+ compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&denver_0 &denver_1>;
+ };
+
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
+ };
+
thermal-zones {
a57 {
polling-delay = <0>;
--
2.28.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: tegra186: Add missing CPU PMUs
2020-10-13 9:58 [PATCH] arm64: tegra186: Add missing CPU PMUs Marc Zyngier
@ 2020-11-10 17:36 ` Thierry Reding
2020-11-10 18:08 ` Marc Zyngier
0 siblings, 1 reply; 5+ messages in thread
From: Thierry Reding @ 2020-11-10 17:36 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-tegra, linux-kernel, Rob Herring, Jonathan Hunter,
Nagarjuna Kristam, Sowjanya Komatineni, devicetree
[-- Attachment #1: Type: text/plain, Size: 2142 bytes --]
On Tue, Oct 13, 2020 at 10:58:51AM +0100, Marc Zyngier wrote:
> Add the description of CPU PMUs for both the Denver and A57 clusters,
> which enables the perf subsystem.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++-----
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index fd44545e124d..6bb03668a8d3 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -1321,7 +1321,7 @@ cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu@0 {
> + denver_0: cpu@0 {
> compatible = "nvidia,tegra186-denver";
> device_type = "cpu";
> i-cache-size = <0x20000>;
> @@ -1334,7 +1334,7 @@ cpu@0 {
> reg = <0x000>;
> };
>
> - cpu@1 {
> + denver_1: cpu@1 {
> compatible = "nvidia,tegra186-denver";
> device_type = "cpu";
> i-cache-size = <0x20000>;
> @@ -1347,7 +1347,7 @@ cpu@1 {
> reg = <0x001>;
> };
>
> - cpu@2 {
> + ca57_0: cpu@2 {
> compatible = "arm,cortex-a57";
> device_type = "cpu";
> i-cache-size = <0xC000>;
> @@ -1360,7 +1360,7 @@ cpu@2 {
> reg = <0x100>;
> };
>
> - cpu@3 {
> + ca57_1: cpu@3 {
> compatible = "arm,cortex-a57";
> device_type = "cpu";
> i-cache-size = <0xC000>;
> @@ -1373,7 +1373,7 @@ cpu@3 {
> reg = <0x101>;
> };
>
> - cpu@4 {
> + ca57_2: cpu@4 {
> compatible = "arm,cortex-a57";
> device_type = "cpu";
> i-cache-size = <0xC000>;
> @@ -1386,7 +1386,7 @@ cpu@4 {
> reg = <0x102>;
> };
>
> - cpu@5 {
> + ca57_3: cpu@5 {
> compatible = "arm,cortex-a57";
> device_type = "cpu";
> i-cache-size = <0xC000>;
> @@ -1418,6 +1418,22 @@ L2_A57: l2-cache1 {
> };
> };
>
> + pmu_denver {
> + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
checkpatch complains that this isn't documented. Did I miss the DT
bindings patch or do we not have one for this?
Thierry
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: tegra186: Add missing CPU PMUs
2020-11-10 17:36 ` Thierry Reding
@ 2020-11-10 18:08 ` Marc Zyngier
2020-11-10 18:22 ` Thierry Reding
0 siblings, 1 reply; 5+ messages in thread
From: Marc Zyngier @ 2020-11-10 18:08 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-tegra, linux-kernel, Rob Herring, Jonathan Hunter,
Nagarjuna Kristam, Sowjanya Komatineni, devicetree
On 2020-11-10 17:36, Thierry Reding wrote:
> On Tue, Oct 13, 2020 at 10:58:51AM +0100, Marc Zyngier wrote:
>> Add the description of CPU PMUs for both the Denver and A57 clusters,
>> which enables the perf subsystem.
>>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
[...]
>>
>> + pmu_denver {
>> + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
>
> checkpatch complains that this isn't documented. Did I miss the DT
> bindings patch or do we not have one for this?
We don't. But I don't think adding a compatible string for each
and every micro-architecture makes much sense unless we have something
useful to add to that compatible string. Such as a full description
of the implementation specific events.
Thanks,
M.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: tegra186: Add missing CPU PMUs
2020-11-10 18:08 ` Marc Zyngier
@ 2020-11-10 18:22 ` Thierry Reding
2020-11-10 18:27 ` Marc Zyngier
0 siblings, 1 reply; 5+ messages in thread
From: Thierry Reding @ 2020-11-10 18:22 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-tegra, linux-kernel, Rob Herring, Jonathan Hunter,
Nagarjuna Kristam, Sowjanya Komatineni, devicetree
[-- Attachment #1: Type: text/plain, Size: 950 bytes --]
On Tue, Nov 10, 2020 at 06:08:31PM +0000, Marc Zyngier wrote:
> On 2020-11-10 17:36, Thierry Reding wrote:
> > On Tue, Oct 13, 2020 at 10:58:51AM +0100, Marc Zyngier wrote:
> > > Add the description of CPU PMUs for both the Denver and A57 clusters,
> > > which enables the perf subsystem.
> > >
> > > Signed-off-by: Marc Zyngier <maz@kernel.org>
>
> [...]
>
> > >
> > > + pmu_denver {
> > > + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
> >
> > checkpatch complains that this isn't documented. Did I miss the DT
> > bindings patch or do we not have one for this?
>
> We don't. But I don't think adding a compatible string for each
> and every micro-architecture makes much sense unless we have something
> useful to add to that compatible string. Such as a full description
> of the implementation specific events.
I'm wondering if this isn't going to upset Rob's json-schema bot and
make him mad.
Thierry
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: tegra186: Add missing CPU PMUs
2020-11-10 18:22 ` Thierry Reding
@ 2020-11-10 18:27 ` Marc Zyngier
0 siblings, 0 replies; 5+ messages in thread
From: Marc Zyngier @ 2020-11-10 18:27 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-tegra, linux-kernel, Rob Herring, Jonathan Hunter,
Nagarjuna Kristam, Sowjanya Komatineni, devicetree
On 2020-11-10 18:22, Thierry Reding wrote:
> On Tue, Nov 10, 2020 at 06:08:31PM +0000, Marc Zyngier wrote:
>> On 2020-11-10 17:36, Thierry Reding wrote:
>> > On Tue, Oct 13, 2020 at 10:58:51AM +0100, Marc Zyngier wrote:
>> > > Add the description of CPU PMUs for both the Denver and A57 clusters,
>> > > which enables the perf subsystem.
>> > >
>> > > Signed-off-by: Marc Zyngier <maz@kernel.org>
>>
>> [...]
>>
>> > >
>> > > + pmu_denver {
>> > > + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
>> >
>> > checkpatch complains that this isn't documented. Did I miss the DT
>> > bindings patch or do we not have one for this?
>>
>> We don't. But I don't think adding a compatible string for each
>> and every micro-architecture makes much sense unless we have something
>> useful to add to that compatible string. Such as a full description
>> of the implementation specific events.
>
> I'm wondering if this isn't going to upset Rob's json-schema bot and
> make him mad.
Rob going mad? Never! ;-)
If you *really* want it, I'll respin this patch with the Denver
compatible
added to Documentation/devicetree/bindings/arm/pmu.yaml.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-11-10 17:36 ` Thierry Reding
2020-11-10 18:08 ` Marc Zyngier
2020-11-10 18:22 ` Thierry Reding
2020-11-10 18:27 ` Marc Zyngier
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