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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH v1] pinctrl: intel: Add Intel Alder Lake pin controller support
Date: Thu, 29 Oct 2020 12:00:38 +0200	[thread overview]
Message-ID: <20201029100038.GE4077@smile.fi.intel.com> (raw)
In-Reply-To: <20201029080827.GN2495@lahna.fi.intel.com>

On Thu, Oct 29, 2020 at 10:08:27AM +0200, Mika Westerberg wrote:

> I think the $subject should say "Alder Lake-S" as this is for -S
> variant.

OK!

...

> > @@ -158,4 +166,5 @@ config PINCTRL_TIGERLAKE
> >  	help
> >  	  This pinctrl driver provides an interface that allows configuring
> >  	  of Intel Tiger Lake PCH pins and using them as GPIOs.
> > +
> 
> Is this intentional ws change?

I guess it was intentional at some point, but not strictly related to this new
driver. I can split it out.

> >  endif
> 
> Otherwise looks good to me.

I'll send v2 soon.

-- 
With Best Regards,
Andy Shevchenko



      reply	other threads:[~2020-10-29  9:59 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-26 19:25 [PATCH v1] pinctrl: intel: Add Intel Alder Lake pin controller support Andy Shevchenko
2020-10-29  8:08 ` Mika Westerberg
2020-10-29 10:00   ` Andy Shevchenko [this message]

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