From: Pratyush Yadav <p.yadav@ti.com>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: <broonie@kernel.org>, <vigneshr@ti.com>,
<tudor.ambarus@microchip.com>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <robh+dt@kernel.org>,
<devicetree@vger.kernel.org>, <miquel.raynal@bootlin.com>,
<simon.k.r.goldschmidt@gmail.com>, <dinguyen@kernel.org>,
<richard@nod.at>, <cheol.yong.kim@intel.com>,
<qi-ming.wu@intel.com>
Subject: Re: [PATCH v6 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
Date: Tue, 3 Nov 2020 21:39:42 +0530 [thread overview]
Message-ID: <20201103160834.mfbasmmlgsptnl5l@ti.com> (raw)
In-Reply-To: <20201030053153.5319-3-vadivel.muruganx.ramuthevar@linux.intel.com>
On 30/10/20 01:31PM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
> Direct Access Controller(DAC).
>
> This patch adds a quirk to disable the Direct Access Controller
> for data transfer instead it uses indirect data transfer.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index d7b10c46fa70..6d6f7c440ece 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -1107,6 +1107,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
> writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>
> cqspi_controller_enable(cqspi, 1);
> +
> + /* Disable direct access controller */
> + if (!cqspi->use_direct_mode) {
> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> + }
You did not address my comment here from last time around [0]. Please
replace this hunk with the one below and test it. Also mention in the
commit message that the DAC bit resets to 1 so there is no need to
explicitly set it.
--- 8< ---
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index d7ad8b198a11..d2c5d448a944 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2156,10 +2156,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
- /* Enable Direct Access Controller */
- reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
- writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ /* Disable Direct Access Controller */
+ if (!cqspi->use_dac_mode) {
+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ }
cqspi_controller_enable(cqspi, 1);
}
--- >8 ---
Same disclaimer as last time: not tested at all.
[0] https://lore.kernel.org/linux-spi/20201022090146.2uj5gfx73dsfumjl@ti.com/
PS: Please Cc me in the next revision. I missed 3 revisions in between
because I'm not subscribed to this list. Otherwise I would have sent
this much sooner :-)
> }
>
> static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
> @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
> .quirks = CQSPI_NEEDS_WR_DELAY,
> };
>
> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .quirks = CQSPI_DISABLE_DAC_MODE,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
> },
> {
> .compatible = "intel,lgm-qspi",
> + .data = &intel_lgm_qspi,
> },
> { /* end of table */ }
> };
> --
> 2.11.0
>
--
Regards,
Pratyush Yadav
Texas Instruments India
next prev parent reply other threads:[~2020-11-03 16:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-30 5:31 [PATCH v6 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-11-03 16:09 ` Pratyush Yadav [this message]
2020-11-04 9:18 ` Ramuthevar, Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
2020-11-05 7:11 ` Linus Walleij
2020-11-06 4:33 ` Ramuthevar, Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-30 15:18 ` Rob Herring
2020-11-02 5:59 ` Ramuthevar, Vadivel MuruganX
2020-11-04 22:02 ` Rob Herring
2020-11-09 1:40 ` Ramuthevar, Vadivel MuruganX
2020-10-30 5:31 ` [PATCH v6 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-11-04 22:03 ` Rob Herring
2020-11-09 1:49 ` Ramuthevar, Vadivel MuruganX
2020-11-09 15:15 ` Rob Herring
2020-11-10 5:21 ` Ramuthevar, Vadivel MuruganX
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