From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: x86@kernel.org, linux-sgx@vger.kernel.org
Cc: linux-kernel@vger.kernel.org,
Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>,
Jethro Beekman <jethro@fortanix.com>,
Darren Kenny <darren.kenny@oracle.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com,
asapek@google.com, bp@alien8.de, cedric.xing@intel.com,
chenalexchen@google.com, conradparker@google.com,
cyhanish@google.com, dave.hansen@intel.com,
haitao.huang@intel.com, kai.huang@intel.com, kai.svahn@intel.com,
kmoy@google.com, ludloff@google.com, luto@kernel.org,
nhorman@redhat.com, npmccallum@redhat.com, puiterwijk@redhat.com,
rientjes@google.com, tglx@linutronix.de, yaozhangx@google.com,
mikko.ylinen@intel.com
Subject: [PATCH v40 02/24] x86/sgx: Add wrappers for ENCLS functions
Date: Wed, 4 Nov 2020 16:54:08 +0200 [thread overview]
Message-ID: <20201104145430.300542-3-jarkko.sakkinen@linux.intel.com> (raw)
In-Reply-To: <20201104145430.300542-1-jarkko.sakkinen@linux.intel.com>
ENCLS is the userspace instruction which wraps virtually all
unprivileged SGX functionality for managing enclaves. It is essentially
the ioctl() of instructions with each function implementing different
SGX-related functionality.
Add macros to wrap the ENCLS functionality. There are two main groups,
one for functions which do not return error codes and a “ret_” set for
those that do.
ENCLS functions are documented in Intel SDM section 36.6.
Acked-by: Jethro Beekman <jethro@fortanix.com>
Tested-by: Darren Kenny <darren.kenny@oracle.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
arch/x86/kernel/cpu/sgx/encls.h | 231 ++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
create mode 100644 arch/x86/kernel/cpu/sgx/encls.h
diff --git a/arch/x86/kernel/cpu/sgx/encls.h b/arch/x86/kernel/cpu/sgx/encls.h
new file mode 100644
index 000000000000..443188fe7e70
--- /dev/null
+++ b/arch/x86/kernel/cpu/sgx/encls.h
@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _X86_ENCLS_H
+#define _X86_ENCLS_H
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/rwsem.h>
+#include <linux/types.h>
+#include <asm/asm.h>
+#include <asm/traps.h>
+#include "sgx.h"
+
+enum sgx_encls_function {
+ ECREATE = 0x00,
+ EADD = 0x01,
+ EINIT = 0x02,
+ EREMOVE = 0x03,
+ EDGBRD = 0x04,
+ EDGBWR = 0x05,
+ EEXTEND = 0x06,
+ ELDU = 0x08,
+ EBLOCK = 0x09,
+ EPA = 0x0A,
+ EWB = 0x0B,
+ ETRACK = 0x0C,
+};
+
+/**
+ * ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
+ *
+ * ENCLS has its own (positive value) error codes and also generates
+ * ENCLS specific #GP and #PF faults. And the ENCLS values get munged
+ * with system error codes as everything percolates back up the stack.
+ * Unfortunately (for us), we need to precisely identify each unique
+ * error code, e.g. the action taken if EWB fails varies based on the
+ * type of fault and on the exact SGX error code, i.e. we can't simply
+ * convert all faults to -EFAULT.
+ *
+ * To make all three error types coexist, we set bit 30 to identify an
+ * ENCLS fault. Bit 31 (technically bits N:31) is used to differentiate
+ * between positive (faults and SGX error codes) and negative (system
+ * error codes) values.
+ */
+#define ENCLS_FAULT_FLAG 0x40000000
+
+/* Retrieve the encoded trapnr from the specified return code. */
+#define ENCLS_TRAPNR(r) ((r) & ~ENCLS_FAULT_FLAG)
+
+/* Issue a WARN() about an ENCLS function. */
+#define ENCLS_WARN(r, name) { \
+ do { \
+ int _r = (r); \
+ WARN_ONCE(_r, "%s returned %d (0x%x)\n", (name), _r, _r); \
+ } while (0); \
+}
+
+/**
+ * encls_failed() - Check if an ENCLS function failed
+ * @ret: the return value of an ENCLS function call
+ *
+ * Check if an ENCLS function failed. This happens when the function causes a
+ * fault that is not caused by an EPCM conflict or when the function returns a
+ * non-zero value.
+ */
+static inline bool encls_failed(int ret)
+{
+ if (ret & ENCLS_FAULT_FLAG)
+ return ENCLS_TRAPNR(ret) != X86_TRAP_PF;
+
+ return !!ret;
+}
+
+/**
+ * __encls_ret_N - encode an ENCLS function that returns an error code in EAX
+ * @rax: function number
+ * @inputs: asm inputs for the function
+ *
+ * Emit assembly for an ENCLS function that returns an error code, e.g. EREMOVE.
+ * And because SGX isn't complex enough as it is, function that return an error
+ * code also modify flags.
+ *
+ * Return:
+ * 0 on success,
+ * SGX error code on failure
+ */
+#define __encls_ret_N(rax, inputs...) \
+ ({ \
+ int ret; \
+ asm volatile( \
+ "1: .byte 0x0f, 0x01, 0xcf;\n\t" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: orl $"__stringify(ENCLS_FAULT_FLAG)",%%eax\n" \
+ " jmp 2b\n" \
+ ".previous\n" \
+ _ASM_EXTABLE_FAULT(1b, 3b) \
+ : "=a"(ret) \
+ : "a"(rax), inputs \
+ : "memory", "cc"); \
+ ret; \
+ })
+
+#define __encls_ret_1(rax, rcx) \
+ ({ \
+ __encls_ret_N(rax, "c"(rcx)); \
+ })
+
+#define __encls_ret_2(rax, rbx, rcx) \
+ ({ \
+ __encls_ret_N(rax, "b"(rbx), "c"(rcx)); \
+ })
+
+#define __encls_ret_3(rax, rbx, rcx, rdx) \
+ ({ \
+ __encls_ret_N(rax, "b"(rbx), "c"(rcx), "d"(rdx)); \
+ })
+
+/**
+ * __encls_N - encode an ENCLS function that doesn't return an error code
+ * @rax: function number
+ * @rbx_out: optional output variable
+ * @inputs: asm inputs for the function
+ *
+ * Emit assembly for an ENCLS function that does not return an error code, e.g.
+ * ECREATE. Leaves without error codes either succeed or fault. @rbx_out is an
+ * optional parameter for use by EDGBRD, which returns the requested value in
+ * RBX.
+ *
+ * Return:
+ * 0 on success,
+ * trapnr with ENCLS_FAULT_FLAG set on fault
+ */
+#define __encls_N(rax, rbx_out, inputs...) \
+ ({ \
+ int ret; \
+ asm volatile( \
+ "1: .byte 0x0f, 0x01, 0xcf;\n\t" \
+ " xor %%eax,%%eax;\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: orl $"__stringify(ENCLS_FAULT_FLAG)",%%eax\n" \
+ " jmp 2b\n" \
+ ".previous\n" \
+ _ASM_EXTABLE_FAULT(1b, 3b) \
+ : "=a"(ret), "=b"(rbx_out) \
+ : "a"(rax), inputs \
+ : "memory"); \
+ ret; \
+ })
+
+#define __encls_2(rax, rbx, rcx) \
+ ({ \
+ unsigned long ign_rbx_out; \
+ __encls_N(rax, ign_rbx_out, "b"(rbx), "c"(rcx)); \
+ })
+
+#define __encls_1_1(rax, data, rcx) \
+ ({ \
+ unsigned long rbx_out; \
+ int ret = __encls_N(rax, rbx_out, "c"(rcx)); \
+ if (!ret) \
+ data = rbx_out; \
+ ret; \
+ })
+
+static inline int __ecreate(struct sgx_pageinfo *pginfo, void *secs)
+{
+ return __encls_2(ECREATE, pginfo, secs);
+}
+
+static inline int __eextend(void *secs, void *addr)
+{
+ return __encls_2(EEXTEND, secs, addr);
+}
+
+static inline int __eadd(struct sgx_pageinfo *pginfo, void *addr)
+{
+ return __encls_2(EADD, pginfo, addr);
+}
+
+static inline int __einit(void *sigstruct, void *token, void *secs)
+{
+ return __encls_ret_3(EINIT, sigstruct, secs, token);
+}
+
+static inline int __eremove(void *addr)
+{
+ return __encls_ret_1(EREMOVE, addr);
+}
+
+static inline int __edbgwr(void *addr, unsigned long *data)
+{
+ return __encls_2(EDGBWR, *data, addr);
+}
+
+static inline int __edbgrd(void *addr, unsigned long *data)
+{
+ return __encls_1_1(EDGBRD, *data, addr);
+}
+
+static inline int __etrack(void *addr)
+{
+ return __encls_ret_1(ETRACK, addr);
+}
+
+static inline int __eldu(struct sgx_pageinfo *pginfo, void *addr,
+ void *va)
+{
+ return __encls_ret_3(ELDU, pginfo, addr, va);
+}
+
+static inline int __eblock(void *addr)
+{
+ return __encls_ret_1(EBLOCK, addr);
+}
+
+static inline int __epa(void *addr)
+{
+ unsigned long rbx = SGX_PAGE_TYPE_VA;
+
+ return __encls_2(EPA, rbx, addr);
+}
+
+static inline int __ewb(struct sgx_pageinfo *pginfo, void *addr,
+ void *va)
+{
+ return __encls_ret_3(EWB, pginfo, addr, va);
+}
+
+#endif /* _X86_ENCLS_H */
--
2.27.0
next prev parent reply other threads:[~2020-11-04 14:54 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 14:54 [PATCH v40 00/24] Intel SGX foundations Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 01/24] x86/sgx: Add SGX architectural data structures Jarkko Sakkinen
2020-11-04 14:54 ` Jarkko Sakkinen [this message]
2020-11-04 14:54 ` [PATCH v40 03/24] x86/sgx: Initialize metadata for Enclave Page Cache (EPC) sections Jarkko Sakkinen
2020-11-04 18:21 ` Borislav Petkov
2020-11-04 19:04 ` Jarkko Sakkinen
2020-11-04 19:09 ` Jarkko Sakkinen
2020-11-04 19:12 ` Borislav Petkov
2020-11-04 14:54 ` [PATCH v40 04/24] x86/cpufeatures: x86/msr: Add Intel SGX hardware bits Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 05/24] x86/cpufeatures: x86/msr: Add Intel SGX Launch Control " Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 06/24] x86/mm: x86/sgx: Signal SIGSEGV with PF_SGX Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 07/24] x86/cpu/intel: Detect SGX support Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 08/24] x86/cpu/intel: Add nosgx kernel parameter Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 09/24] x86/sgx: Add SGX page allocator functions Jarkko Sakkinen
2020-11-05 15:08 ` Borislav Petkov
2020-11-04 14:54 ` [PATCH v40 10/24] mm: Add 'mprotect' hook to struct vm_operations_struct Jarkko Sakkinen
2020-11-05 16:04 ` Borislav Petkov
2020-11-05 17:33 ` Dave Hansen
2020-11-06 10:04 ` Mel Gorman
2020-11-06 16:51 ` Jarkko Sakkinen
2020-11-06 20:37 ` Borislav Petkov
2020-11-06 22:04 ` Jarkko Sakkinen
2020-11-06 22:31 ` Borislav Petkov
2020-11-06 17:43 ` Dr. Greg
2020-11-06 17:54 ` Dave Hansen
2020-11-07 15:09 ` Dr. Greg
2020-11-07 19:16 ` Dave Hansen
2020-11-12 20:58 ` Dr. Greg
2020-11-12 21:31 ` Dave Hansen
2020-11-12 22:41 ` Andy Lutomirski
2020-11-16 18:00 ` Dr. Greg
2020-11-19 1:39 ` Haitao Huang
2020-11-20 17:31 ` Dr. Greg
2020-11-15 18:59 ` Dr. Greg
2020-11-06 21:13 ` Matthew Wilcox
2020-11-06 21:23 ` Dave Hansen
2020-11-07 15:27 ` Dr. Greg
2020-11-04 14:54 ` [PATCH v40 11/24] x86/sgx: Add SGX misc driver interface Jarkko Sakkinen
2020-11-05 1:10 ` Jarkko Sakkinen
2020-11-05 1:16 ` Jarkko Sakkinen
2020-11-05 16:05 ` Borislav Petkov
2020-11-05 17:57 ` Jarkko Sakkinen
2020-11-05 18:10 ` Borislav Petkov
2020-11-06 16:07 ` Jarkko Sakkinen
2020-11-06 17:09 ` Borislav Petkov
2020-11-06 22:01 ` Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 12/24] x86/sgx: Add SGX_IOC_ENCLAVE_CREATE Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 13/24] x86/sgx: Add SGX_IOC_ENCLAVE_ADD_PAGES Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 14/24] x86/sgx: Add SGX_IOC_ENCLAVE_INIT Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 15/24] x86/sgx: Add SGX_IOC_ENCLAVE_PROVISION Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 16/24] x86/vdso: Add support for exception fixup in vDSO functions Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 17/24] x86/fault: Add helper function to sanitize error code Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 18/24] x86/traps: Attempt to fixup exceptions in vDSO before signaling Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 19/24] x86/vdso: Implement a vDSO for Intel SGX enclave call Jarkko Sakkinen
2020-11-08 18:24 ` Jethro Beekman
2020-11-08 20:08 ` Jethro Beekman
2020-11-08 20:26 ` Dave Hansen
2020-11-08 20:20 ` Jethro Beekman
2020-11-08 20:30 ` Dave Hansen
2020-11-04 14:54 ` [PATCH v40 20/24] selftests/x86: Add a selftest for SGX Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 21/24] x86/sgx: Add a page reclaimer Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 22/24] x86/sgx: Add ptrace() support for the SGX driver Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 23/24] docs: x86/sgx: Document SGX kernel architecture Jarkko Sakkinen
2020-11-04 14:54 ` [PATCH v40 24/24] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
2020-11-08 20:48 ` [PATCH v40 00/24] Intel SGX foundations Jethro Beekman
[not found] ` <20201108035630.11540-1-hdanton@sina.com>
2020-11-09 19:59 ` [PATCH v40 21/24] x86/sgx: Add a page reclaimer Jarkko Sakkinen
2020-11-21 15:12 ` [PATCH v40 00/24] Intel SGX foundations Dr. Greg
2020-11-21 16:25 ` Dave Hansen
2020-11-24 10:55 ` Dr. Greg
2020-11-24 17:49 ` Andy Lutomirski
2020-11-21 18:36 ` Andy Lutomirski
2020-11-24 18:40 ` Dr. Greg
2020-11-24 21:57 ` Andy Lutomirski
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