* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-07 11:52 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards 周琰杰 (Zhou Yanjie)
@ 2020-11-07 19:03 ` H. Nikolaus Schaller
2020-11-08 12:46 ` Zhou Yanjie
2020-11-09 23:30 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards Paul Cercueil
2020-11-09 23:37 ` Paul Cercueil
2 siblings, 1 reply; 16+ messages in thread
From: H. Nikolaus Schaller @ 2020-11-07 19:03 UTC (permalink / raw)
To: "周琰杰 (Zhou Yanjie)"
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>
> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1000-Neo.
> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1830-Neo.
>
> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Comments below for CI20 / jz4780 only.
I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
Maybe the SMP hacks are in the way and I have to remove them first or try on top
of v5.9.y
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
> 6 files changed, 267 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
> index 75f5bfbf2c37..b31054a41754 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -93,6 +93,15 @@
> clock-frequency = <48000000>;
> };
>
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
> + * precision.
> + */
> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
> +};
> +
ok
> &mmc0 {
> status = "okay";
>
> @@ -396,6 +405,13 @@
> status = "okay";
> };
>
> +&otg {
> + status = "okay";
> +
> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
> + assigned-clock-rates = <48000000>;
> +};
> +
ok
> &pinctrl {
> pins_uart0: uart0 {
> function = "uart0";
> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> index 22a1066d637b..44d47d12db12 100644
> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1000.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1000_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart2 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart2>;
> };
>
> +&ssi {
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpc>;
> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart2: uart2 {
> function = "uart2";
> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> index 640f96c00d63..7a56e344e429 100644
> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1830.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi0: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1830_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart1 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart1>;
> };
>
> +&ssi0 {
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpb>;
> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart1: uart1 {
> function = "uart1";
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index dfb5a7e1bb21..8837147e5a84 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -61,13 +61,30 @@
> };
>
> cgu: jz4780-cgu@10000000 {
> - compatible = "ingenic,jz4780-cgu";
> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
> +
> + #clock-cells = <1>;
>
> clocks = <&ext>, <&rtc>;
> clock-names = "ext", "rtc";
>
> - #clock-cells = <1>;
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,jz4780-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu JZ4780_CLK_OTG1>;
> +
> + #phy-cells = <0>;
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,jz4780-rng";
> + reg = <0xd8 0x8>;
> + };
> };
>
> tcu: timer@10002000 {
> @@ -494,4 +511,24 @@
>
> status = "disabled";
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu JZ4780_CLK_UHC>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
I had tested with 256 before and do not see a reason why 768 should not work as well.
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index 1f1f896dd1f7..854fac58f45e 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -52,13 +52,43 @@
> };
>
> cgu: x1000-cgu@10000000 {
> - compatible = "ingenic,x1000-cgu";
> + compatible = "ingenic,x1000-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1000-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1000_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,x1000-rng";
> + reg = <0xd8 0x8>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1000_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <3>;
> };
>
> tcu: timer@10002000 {
> @@ -323,4 +353,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1000-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1000_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index b05dac3ae308..4831350efdf2 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -52,13 +52,38 @@
> };
>
> cgu: x1830-cgu@10000000 {
> - compatible = "ingenic,x1830-cgu";
> + compatible = "ingenic,x1830-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1830-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1830_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1830_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <4>;
> };
>
> tcu: timer@10002000 {
> @@ -236,6 +261,13 @@
> status = "disabled";
> };
>
> + dtrng: trng@10072000 {
> + compatible = "ingenic,x1830-dtrng";
> + reg = <0x10072000 0xc>;
> +
> + clocks = <&cgu X1830_CLK_DTRNG>;
> + };
> +
> pdma: dma-controller@13420000 {
> compatible = "ingenic,x1830-dma";
> reg = <0x13420000 0x400
> @@ -311,4 +343,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1830-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1830_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-07 19:03 ` H. Nikolaus Schaller
@ 2020-11-08 12:46 ` Zhou Yanjie
2020-11-08 14:35 ` H. Nikolaus Schaller
0 siblings, 1 reply; 16+ messages in thread
From: Zhou Yanjie @ 2020-11-08 12:46 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Hello Nikolaus,
On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
>> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>>
>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1000-Neo.
>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1830-Neo.
>>
>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
> Comments below for CI20 / jz4780 only.
>
> I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
> Maybe the SMP hacks are in the way and I have to remove them first or try on top
> of v5.9.y
SMP is not available on the mainline now, so the previous SMP patch
needs to be removed. The new SMP patch will take some time because it
needs to ensure support for the new X2000 processor.
Thanks and best regards!
>
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> ---
>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 75f5bfbf2c37..b31054a41754 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -93,6 +93,15 @@
>> clock-frequency = <48000000>;
>> };
>>
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>> +};
>> +
> ok
>
>> &mmc0 {
>> status = "okay";
>>
>> @@ -396,6 +405,13 @@
>> status = "okay";
>> };
>>
>> +&otg {
>> + status = "okay";
>> +
>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>> + assigned-clock-rates = <48000000>;
>> +};
>> +
> ok
>
>> &pinctrl {
>> pins_uart0: uart0 {
>> function = "uart0";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> index 22a1066d637b..44d47d12db12 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1000.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart2 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart2>;
>> };
>>
>> +&ssi {
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpc>;
>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart2: uart2 {
>> function = "uart2";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> index 640f96c00d63..7a56e344e429 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1830.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi0: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart1 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart1>;
>> };
>>
>> +&ssi0 {
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpb>;
>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart1: uart1 {
>> function = "uart1";
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index dfb5a7e1bb21..8837147e5a84 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -61,13 +61,30 @@
>> };
>>
>> cgu: jz4780-cgu@10000000 {
>> - compatible = "ingenic,jz4780-cgu";
>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>> +
>> + #clock-cells = <1>;
>>
>> clocks = <&ext>, <&rtc>;
>> clock-names = "ext", "rtc";
>>
>> - #clock-cells = <1>;
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,jz4780-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>> +
>> + #phy-cells = <0>;
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,jz4780-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> };
>>
>> tcu: timer@10002000 {
>> @@ -494,4 +511,24 @@
>>
>> status = "disabled";
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu JZ4780_CLK_UHC>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
> I had tested with 256 before and do not see a reason why 768 should not work as well.
>
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> index 1f1f896dd1f7..854fac58f45e 100644
>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -52,13 +52,43 @@
>> };
>>
>> cgu: x1000-cgu@10000000 {
>> - compatible = "ingenic,x1000-cgu";
>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1000-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,x1000-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1000_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <3>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -323,4 +353,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1000_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> index b05dac3ae308..4831350efdf2 100644
>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> @@ -52,13 +52,38 @@
>> };
>>
>> cgu: x1830-cgu@10000000 {
>> - compatible = "ingenic,x1830-cgu";
>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1830-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1830_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <4>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -236,6 +261,13 @@
>> status = "disabled";
>> };
>>
>> + dtrng: trng@10072000 {
>> + compatible = "ingenic,x1830-dtrng";
>> + reg = <0x10072000 0xc>;
>> +
>> + clocks = <&cgu X1830_CLK_DTRNG>;
>> + };
>> +
>> pdma: dma-controller@13420000 {
>> compatible = "ingenic,x1830-dma";
>> reg = <0x13420000 0x400
>> @@ -311,4 +343,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1830_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> --
>> 2.11.0
>>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-08 12:46 ` Zhou Yanjie
@ 2020-11-08 14:35 ` H. Nikolaus Schaller
2020-11-08 15:13 ` Zhou Yanjie
0 siblings, 1 reply; 16+ messages in thread
From: H. Nikolaus Schaller @ 2020-11-08 14:35 UTC (permalink / raw)
To: Zhou Yanjie
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
> Am 08.11.2020 um 13:46 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>
> Hello Nikolaus,
>
> On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
>>> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>>>
>>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>>> nodes for CU1000-Neo.
>>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>>> nodes for CU1830-Neo.
>>>
>>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>> Comments below for CI20 / jz4780 only.
>>
>> I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
>> Maybe the SMP hacks are in the way and I have to remove them first or try on top
>> of v5.9.y
>
>
> SMP is not available on the mainline now, so the previous SMP patch needs to be removed.
I have tried with CONFIG_SMP disabled and now I can boot my v5.10-rc2 (plus local patches).
And can confirm that the OTG port works.
(BTW: dm9000 defers probing forever but that is an unrelated issue).
> The new SMP patch will take some time because it needs to ensure support for the new X2000 processor.
Ok, I see. It is a little sad since it works find until 5.9 but now is broken and means we
have to test v5.10ff with only one processor. Any hints what should be hacked to make it
work until a final solution becomes available in upstream?
>
>
> Thanks and best regards!
If you like you can add my
Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
to this patch.
>
>
>>
>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>>> ---
>>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
>>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
>>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
>>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>>> index 75f5bfbf2c37..b31054a41754 100644
>>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>>> @@ -93,6 +93,15 @@
>>> clock-frequency = <48000000>;
>>> };
>>>
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>>> +};
>>> +
>> ok
>>
>>> &mmc0 {
>>> status = "okay";
>>>
>>> @@ -396,6 +405,13 @@
>>> status = "okay";
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +
>>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>>> + assigned-clock-rates = <48000000>;
>>> +};
>>> +
>> ok
>>
>>> &pinctrl {
>>> pins_uart0: uart0 {
>>> function = "uart0";
>>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> index 22a1066d637b..44d47d12db12 100644
>>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> @@ -3,7 +3,7 @@
>>>
>>> #include "x1000.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>
>>> / {
>>> @@ -31,6 +31,18 @@
>>> };
>>> };
>>>
>>> + ssi: spi-gpio {
>>> + compatible = "spi-gpio";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + num-chipselects = <1>;
>>> +
>>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>>> + };
>>> +
>>> wlan_pwrseq: msc1-pwrseq {
>>> compatible = "mmc-pwrseq-simple";
>>>
>>> @@ -43,13 +55,19 @@
>>> clock-frequency = <24000000>;
>>> };
>>>
>>> -&tcu {
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>>> +};
>>> +
>>> +&ost {
>>> /* 1500 kHz for the system timer and clocksource */
>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>> assigned-clock-rates = <1500000>, <1500000>;
>>> -
>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>> - ingenic,pwm-channels-mask = <0xfa>;
>>> };
>>>
>>> &uart2 {
>>> @@ -59,6 +77,32 @@
>>> pinctrl-0 = <&pins_uart2>;
>>> };
>>>
>>> +&ssi {
>>> + status = "okay";
>>> +
>>> + spi-max-frequency = <50000000>;
>>> +
>>> + sc16is752: expander@0 {
>>> + compatible = "nxp,sc16is752";
>>> + reg = <0>; /* CE0 */
>>> + spi-max-frequency = <4000000>;
>>> +
>>> + clocks = <&exclk_sc16is752>;
>>> +
>>> + interrupt-parent = <&gpc>;
>>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>>> +
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> +
>>> + exclk_sc16is752: sc16is752 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <48000000>;
>>> + };
>>> + };
>>> +};
>>> +
>>> &i2c0 {
>>> status = "okay";
>>>
>>> @@ -135,6 +179,10 @@
>>> };
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +};
>>> +
>>> &pinctrl {
>>> pins_uart2: uart2 {
>>> function = "uart2";
>>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> index 640f96c00d63..7a56e344e429 100644
>>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> @@ -3,7 +3,7 @@
>>>
>>> #include "x1830.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>
>>> / {
>>> @@ -31,6 +31,18 @@
>>> };
>>> };
>>>
>>> + ssi0: spi-gpio {
>>> + compatible = "spi-gpio";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + num-chipselects = <1>;
>>> +
>>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>>> + };
>>> +
>>> wlan_pwrseq: msc1-pwrseq {
>>> compatible = "mmc-pwrseq-simple";
>>>
>>> @@ -43,13 +55,19 @@
>>> clock-frequency = <24000000>;
>>> };
>>>
>>> -&tcu {
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>>> +};
>>> +
>>> +&ost {
>>> /* 1500 kHz for the system timer and clocksource */
>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>> assigned-clock-rates = <1500000>, <1500000>;
>>> -
>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>> - ingenic,pwm-channels-mask = <0xfa>;
>>> };
>>>
>>> &uart1 {
>>> @@ -59,6 +77,32 @@
>>> pinctrl-0 = <&pins_uart1>;
>>> };
>>>
>>> +&ssi0 {
>>> + status = "okay";
>>> +
>>> + spi-max-frequency = <50000000>;
>>> +
>>> + sc16is752: expander@0 {
>>> + compatible = "nxp,sc16is752";
>>> + reg = <0>; /* CE0 */
>>> + spi-max-frequency = <4000000>;
>>> +
>>> + clocks = <&exclk_sc16is752>;
>>> +
>>> + interrupt-parent = <&gpb>;
>>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>> +
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> +
>>> + exclk_sc16is752: sc16is752 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <48000000>;
>>> + };
>>> + };
>>> +};
>>> +
>>> &i2c0 {
>>> status = "okay";
>>>
>>> @@ -135,6 +179,10 @@
>>> };
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +};
>>> +
>>> &pinctrl {
>>> pins_uart1: uart1 {
>>> function = "uart1";
>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> index dfb5a7e1bb21..8837147e5a84 100644
>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> @@ -61,13 +61,30 @@
>>> };
>>>
>>> cgu: jz4780-cgu@10000000 {
>>> - compatible = "ingenic,jz4780-cgu";
>>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>> +
>>> + #clock-cells = <1>;
>>>
>>> clocks = <&ext>, <&rtc>;
>>> clock-names = "ext", "rtc";
>>>
>>> - #clock-cells = <1>;
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,jz4780-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>>> +
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + rng: rng@d8 {
>>> + compatible = "ingenic,jz4780-rng";
>>> + reg = <0xd8 0x8>;
>>> + };
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -494,4 +511,24 @@
>>>
>>> status = "disabled";
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu JZ4780_CLK_UHC>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>> I had tested with 256 before and do not see a reason why 768 should not work as well.
>>
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> index 1f1f896dd1f7..854fac58f45e 100644
>>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> @@ -52,13 +52,43 @@
>>> };
>>>
>>> cgu: x1000-cgu@10000000 {
>>> - compatible = "ingenic,x1000-cgu";
>>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>>
>>> #clock-cells = <1>;
>>>
>>> clocks = <&exclk>, <&rtclk>;
>>> clock-names = "ext", "rtc";
>>> +
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,x1000-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>>> +
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + rng: rng@d8 {
>>> + compatible = "ingenic,x1000-rng";
>>> + reg = <0xd8 0x8>;
>>> + };
>>> + };
>>> +
>>> + ost: timer@12000000 {
>>> + compatible = "ingenic,x1000-ost";
>>> + reg = <0x12000000 0x3c>;
>>> +
>>> + #clock-cells = <1>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OST>;
>>> + clock-names = "ost";
>>> +
>>> + interrupt-parent = <&cpuintc>;
>>> + interrupts = <3>;
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -323,4 +353,24 @@
>>> status = "disabled";
>>> };
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OTG>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> index b05dac3ae308..4831350efdf2 100644
>>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> @@ -52,13 +52,38 @@
>>> };
>>>
>>> cgu: x1830-cgu@10000000 {
>>> - compatible = "ingenic,x1830-cgu";
>>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>>
>>> #clock-cells = <1>;
>>>
>>> clocks = <&exclk>, <&rtclk>;
>>> clock-names = "ext", "rtc";
>>> +
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,x1830-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>>> +
>>> + #phy-cells = <0>;
>>> + };
>>> + };
>>> +
>>> + ost: timer@12000000 {
>>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>>> + reg = <0x12000000 0x3c>;
>>> +
>>> + #clock-cells = <1>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OST>;
>>> + clock-names = "ost";
>>> +
>>> + interrupt-parent = <&cpuintc>;
>>> + interrupts = <4>;
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -236,6 +261,13 @@
>>> status = "disabled";
>>> };
>>>
>>> + dtrng: trng@10072000 {
>>> + compatible = "ingenic,x1830-dtrng";
>>> + reg = <0x10072000 0xc>;
>>> +
>>> + clocks = <&cgu X1830_CLK_DTRNG>;
>>> + };
>>> +
>>> pdma: dma-controller@13420000 {
>>> compatible = "ingenic,x1830-dma";
>>> reg = <0x13420000 0x400
>>> @@ -311,4 +343,24 @@
>>> status = "disabled";
>>> };
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OTG>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> --
>>> 2.11.0
>>>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-08 14:35 ` H. Nikolaus Schaller
@ 2020-11-08 15:13 ` Zhou Yanjie
2020-11-08 15:28 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. [and discussion about jz4780 SMP/MMC/Ethernet] H. Nikolaus Schaller
0 siblings, 1 reply; 16+ messages in thread
From: Zhou Yanjie @ 2020-11-08 15:13 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
On 2020/11/8 下午10:35, H. Nikolaus Schaller wrote:
>> Am 08.11.2020 um 13:46 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>>
>> Hello Nikolaus,
>>
>> On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
>>>> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>>>>
>>>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>>>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>>>> nodes for CU1000-Neo.
>>>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>>>> nodes for CU1830-Neo.
>>>>
>>>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>>> Comments below for CI20 / jz4780 only.
>>>
>>> I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
>>> Maybe the SMP hacks are in the way and I have to remove them first or try on top
>>> of v5.9.y
>>
>> SMP is not available on the mainline now, so the previous SMP patch needs to be removed.
> I have tried with CONFIG_SMP disabled and now I can boot my v5.10-rc2 (plus local patches).
> And can confirm that the OTG port works.
Nice to hear it.
> (BTW: dm9000 defers probing forever but that is an unrelated issue).
On my side , it will work normally after selecting CONFIG_JZ4780_EFUSE.
>> The new SMP patch will take some time because it needs to ensure support for the new X2000 processor.
> Ok, I see. It is a little sad since it works find until 5.9 but now is broken and means we
> have to test v5.10ff with only one processor. Any hints what should be hacked to make it
> work until a final solution becomes available in upstream?
I can try to make a version that supports JZ4780 first, and I will send
it to you when it is completed.
>>
>> Thanks and best regards!
> If you like you can add my
>
> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
>
> to this patch.
Sure, I will add it to the next version.
BTW, have you noticed the problem with the MMC of JZ4780? This was first
discovered by Paul. After he told me, I also tested it. When MMC has a
relatively heavy load, there will indeed be many error messages related
to mmcblk, and it is often accompanied by file system damage.
In addition, when doing some heavy work (such as compiling docker
locally), the following warning message will be accompanied (this
problem also exists on X1830):
[ 4361.724410] warn_alloc: 1 callbacks suppressed
[ 4361.724427] go: page allocation failure: order:5,
mode:0x40cc0(GFP_KERNEL|__GFP_COMP), nodemask=(null)
[ 4361.740945] CPU: 0 PID: 6792 Comm: go Tainted: G W 5.10.0-rc1+ #3
[ 4361.748407] Stack : 80960000 801686ec 00000000 80879d2c 00000000
00000001 00000400 801688f8
[ 4361.756845] 00000000 00000000 00000000 810891ca 84405c54
00000001 84405be8 810891ca
[ 4361.765281] 00000000 00000000 8086054c 00000003 00000001
84405abc 00000000 00001cf1
[ 4361.773717] bff4ffd7 2c29ee2f 84405ab4 2e352020 808f0000
80000000 00000000 80860000
[ 4361.782153] 00000000 00000840 00000027 00000001 00000000
80441e34 017f02df 017f031f
[ 4361.790588] ...
[ 4361.793064] Call Trace:
[ 4361.795547] [<80108bd4>] show_stack+0x6c/0x12c
[ 4361.800023] [<80677974>] dump_stack+0xa0/0xd0
[ 4361.804406] [<801f9e30>] warn_alloc+0xa8/0x130
[ 4361.808875] [<801fa7ac>] __alloc_pages_nodemask+0x8d4/0x908
[ 4361.814476] [<802076bc>] ____cache_alloc+0x2b4/0x600
[ 4361.819467] [<80207de8>] __kmalloc+0x90/0x120
[ 4361.823854] [<80296c8c>] proc_sys_call_handler+0xe4/0x230
[ 4361.829280] [<8021901c>] vfs_read+0x12c/0x19c
[ 4361.833662] [<802192c0>] ksys_read+0x80/0xe0
[ 4361.837960] [<80110fb8>] syscall_common+0x34/0x58
[ 4361.842687]
[ 4361.854888] Mem-Info:
[ 4361.858734] active_anon:240 inactive_anon:11673 isolated_anon:0
[ 4361.858734] active_file:104199 inactive_file:53064 isolated_file:0
[ 4361.858734] unevictable:0 dirty:366 writeback:0
[ 4361.858734] slab_reclaimable:15980 slab_unreclaimable:2599
[ 4361.858734] mapped:9755 shmem:3251 pagetables:229 bounce:0
[ 4361.858734] free:67531 free_pcp:71 free_cma:3073
[ 4361.915078] Node 0 active_anon:960kB inactive_anon:46708kB
active_file:416796kB inactive_file:212268kB unevictable:0kB
isolated(anon):0kB isolated(file):0kB mapped:39024kB dirty:1476kB
writeback:0kB shmem:13004kB writeback_tmp:0kB kernel_stack:600kB
all_unreclaimable? no
[ 4361.940604] Normal free:33244kB min:1956kB low:2444kB high:2932kB
reserved_highatomic:0KB active_anon:0kB inactive_anon:156kB
active_file:82176kB inactive_file:47128kB unevictable:0kB
writepending:1228kB present:262144kB managed:239444kB mlocked:0kB
pagetables:908kB bounce:0kB free_pcp:120kB local_pcp:120kB free_cma:12300kB
[ 4361.940612] lowmem_reserve[]: 0 6144 0
[ 4361.974937] HighMem free:236820kB min:512kB low:2116kB high:3720kB
reserved_highatomic:0KB active_anon:960kB inactive_anon:46552kB
active_file:334620kB inactive_file:165140kB unevictable:0kB
writepending:248kB present:786432kB managed:786432kB mlocked:0kB
pagetables:0kB bounce:0kB free_pcp:240kB local_pcp:240kB free_cma:0kB
[ 4361.974944] lowmem_reserve[]: 0 0 0
[ 4362.008189] Normal: 2127*4kB (UMEC) 1508*8kB (UMEC) 472*16kB (UMEC)
96*32kB (UMC) 12*64kB (C) 4*128kB (C) 1*256kB (C) 1*512kB (C) 0*1024kB
0*2048kB 0*4096kB = 33244kB
[ 4362.024364] HighMem: 1441*4kB (UM) 5376*8kB (UM) 3637*16kB (UM)
1210*32kB (UM) 498*64kB (UM) 225*128kB (UM) 69*256kB (UM) 23*512kB (UM)
1*1024kB (M) 0*2048kB 0*4096kB = 236820kB
[ 4362.041152] 160520 total pagecache pages
[ 4362.045838] 0 pages in swap cache
[ 4362.049187] Swap cache stats: add 0, delete 0, find 0/0
[ 4362.055501] Free swap = 0kB
[ 4362.058413] Total swap = 0kB
[ 4362.061315] 262144 pages RAM
[ 4362.065588] 196608 pages HighMem/MovableOnly
[ 4362.069889] 5675 pages reserved
[ 4362.074159] 8192 pages cma reserved
Do you have any idea?
Thanks and best regards!
>>
>>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>>>> ---
>>>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>>>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
>>>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
>>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>>>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
>>>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
>>>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>>>> index 75f5bfbf2c37..b31054a41754 100644
>>>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>>>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>>>> @@ -93,6 +93,15 @@
>>>> clock-frequency = <48000000>;
>>>> };
>>>>
>>>> +&cgu {
>>>> + /*
>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>> + * precision.
>>>> + */
>>>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>>>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>>>> +};
>>>> +
>>> ok
>>>
>>>> &mmc0 {
>>>> status = "okay";
>>>>
>>>> @@ -396,6 +405,13 @@
>>>> status = "okay";
>>>> };
>>>>
>>>> +&otg {
>>>> + status = "okay";
>>>> +
>>>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>>>> + assigned-clock-rates = <48000000>;
>>>> +};
>>>> +
>>> ok
>>>
>>>> &pinctrl {
>>>> pins_uart0: uart0 {
>>>> function = "uart0";
>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>> index 22a1066d637b..44d47d12db12 100644
>>>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>> @@ -3,7 +3,7 @@
>>>>
>>>> #include "x1000.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>
>>>> / {
>>>> @@ -31,6 +31,18 @@
>>>> };
>>>> };
>>>>
>>>> + ssi: spi-gpio {
>>>> + compatible = "spi-gpio";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + num-chipselects = <1>;
>>>> +
>>>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>>>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>>>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>>>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>>>> + };
>>>> +
>>>> wlan_pwrseq: msc1-pwrseq {
>>>> compatible = "mmc-pwrseq-simple";
>>>>
>>>> @@ -43,13 +55,19 @@
>>>> clock-frequency = <24000000>;
>>>> };
>>>>
>>>> -&tcu {
>>>> +&cgu {
>>>> + /*
>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>> + * precision.
>>>> + */
>>>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>>>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>>>> +};
>>>> +
>>>> +&ost {
>>>> /* 1500 kHz for the system timer and clocksource */
>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>> -
>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>> };
>>>>
>>>> &uart2 {
>>>> @@ -59,6 +77,32 @@
>>>> pinctrl-0 = <&pins_uart2>;
>>>> };
>>>>
>>>> +&ssi {
>>>> + status = "okay";
>>>> +
>>>> + spi-max-frequency = <50000000>;
>>>> +
>>>> + sc16is752: expander@0 {
>>>> + compatible = "nxp,sc16is752";
>>>> + reg = <0>; /* CE0 */
>>>> + spi-max-frequency = <4000000>;
>>>> +
>>>> + clocks = <&exclk_sc16is752>;
>>>> +
>>>> + interrupt-parent = <&gpc>;
>>>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>>>> +
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> +
>>>> + exclk_sc16is752: sc16is752 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <48000000>;
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> &i2c0 {
>>>> status = "okay";
>>>>
>>>> @@ -135,6 +179,10 @@
>>>> };
>>>> };
>>>>
>>>> +&otg {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> &pinctrl {
>>>> pins_uart2: uart2 {
>>>> function = "uart2";
>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>> index 640f96c00d63..7a56e344e429 100644
>>>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>> @@ -3,7 +3,7 @@
>>>>
>>>> #include "x1830.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>
>>>> / {
>>>> @@ -31,6 +31,18 @@
>>>> };
>>>> };
>>>>
>>>> + ssi0: spi-gpio {
>>>> + compatible = "spi-gpio";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + num-chipselects = <1>;
>>>> +
>>>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>>>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>>>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>>>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>>>> + };
>>>> +
>>>> wlan_pwrseq: msc1-pwrseq {
>>>> compatible = "mmc-pwrseq-simple";
>>>>
>>>> @@ -43,13 +55,19 @@
>>>> clock-frequency = <24000000>;
>>>> };
>>>>
>>>> -&tcu {
>>>> +&cgu {
>>>> + /*
>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>> + * precision.
>>>> + */
>>>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>>>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>>>> +};
>>>> +
>>>> +&ost {
>>>> /* 1500 kHz for the system timer and clocksource */
>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>> -
>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>> };
>>>>
>>>> &uart1 {
>>>> @@ -59,6 +77,32 @@
>>>> pinctrl-0 = <&pins_uart1>;
>>>> };
>>>>
>>>> +&ssi0 {
>>>> + status = "okay";
>>>> +
>>>> + spi-max-frequency = <50000000>;
>>>> +
>>>> + sc16is752: expander@0 {
>>>> + compatible = "nxp,sc16is752";
>>>> + reg = <0>; /* CE0 */
>>>> + spi-max-frequency = <4000000>;
>>>> +
>>>> + clocks = <&exclk_sc16is752>;
>>>> +
>>>> + interrupt-parent = <&gpb>;
>>>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>>> +
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> +
>>>> + exclk_sc16is752: sc16is752 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <48000000>;
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> &i2c0 {
>>>> status = "okay";
>>>>
>>>> @@ -135,6 +179,10 @@
>>>> };
>>>> };
>>>>
>>>> +&otg {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> &pinctrl {
>>>> pins_uart1: uart1 {
>>>> function = "uart1";
>>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>> index dfb5a7e1bb21..8837147e5a84 100644
>>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>> @@ -61,13 +61,30 @@
>>>> };
>>>>
>>>> cgu: jz4780-cgu@10000000 {
>>>> - compatible = "ingenic,jz4780-cgu";
>>>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>>>> reg = <0x10000000 0x100>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0x0 0x10000000 0x100>;
>>>> +
>>>> + #clock-cells = <1>;
>>>>
>>>> clocks = <&ext>, <&rtc>;
>>>> clock-names = "ext", "rtc";
>>>>
>>>> - #clock-cells = <1>;
>>>> + otg_phy: usb-phy@3c {
>>>> + compatible = "ingenic,jz4780-phy";
>>>> + reg = <0x3c 0x10>;
>>>> +
>>>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>>>> +
>>>> + #phy-cells = <0>;
>>>> + };
>>>> +
>>>> + rng: rng@d8 {
>>>> + compatible = "ingenic,jz4780-rng";
>>>> + reg = <0xd8 0x8>;
>>>> + };
>>>> };
>>>>
>>>> tcu: timer@10002000 {
>>>> @@ -494,4 +511,24 @@
>>>>
>>>> status = "disabled";
>>>> };
>>>> +
>>>> + otg: usb@13500000 {
>>>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>>>> + reg = <0x13500000 0x40000>;
>>>> +
>>>> + interrupt-parent = <&intc>;
>>>> + interrupts = <21>;
>>>> +
>>>> + clocks = <&cgu JZ4780_CLK_UHC>;
>>>> + clock-names = "otg";
>>>> +
>>>> + phys = <&otg_phy>;
>>>> + phy-names = "usb2-phy";
>>>> +
>>>> + g-rx-fifo-size = <768>;
>>> I had tested with 256 before and do not see a reason why 768 should not work as well.
>>>
>>>> + g-np-tx-fifo-size = <256>;
>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> };
>>>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>> index 1f1f896dd1f7..854fac58f45e 100644
>>>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>> @@ -52,13 +52,43 @@
>>>> };
>>>>
>>>> cgu: x1000-cgu@10000000 {
>>>> - compatible = "ingenic,x1000-cgu";
>>>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>>>> reg = <0x10000000 0x100>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>
>>>> #clock-cells = <1>;
>>>>
>>>> clocks = <&exclk>, <&rtclk>;
>>>> clock-names = "ext", "rtc";
>>>> +
>>>> + otg_phy: usb-phy@3c {
>>>> + compatible = "ingenic,x1000-phy";
>>>> + reg = <0x3c 0x10>;
>>>> +
>>>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>>>> +
>>>> + #phy-cells = <0>;
>>>> + };
>>>> +
>>>> + rng: rng@d8 {
>>>> + compatible = "ingenic,x1000-rng";
>>>> + reg = <0xd8 0x8>;
>>>> + };
>>>> + };
>>>> +
>>>> + ost: timer@12000000 {
>>>> + compatible = "ingenic,x1000-ost";
>>>> + reg = <0x12000000 0x3c>;
>>>> +
>>>> + #clock-cells = <1>;
>>>> +
>>>> + clocks = <&cgu X1000_CLK_OST>;
>>>> + clock-names = "ost";
>>>> +
>>>> + interrupt-parent = <&cpuintc>;
>>>> + interrupts = <3>;
>>>> };
>>>>
>>>> tcu: timer@10002000 {
>>>> @@ -323,4 +353,24 @@
>>>> status = "disabled";
>>>> };
>>>> };
>>>> +
>>>> + otg: usb@13500000 {
>>>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>>>> + reg = <0x13500000 0x40000>;
>>>> +
>>>> + interrupt-parent = <&intc>;
>>>> + interrupts = <21>;
>>>> +
>>>> + clocks = <&cgu X1000_CLK_OTG>;
>>>> + clock-names = "otg";
>>>> +
>>>> + phys = <&otg_phy>;
>>>> + phy-names = "usb2-phy";
>>>> +
>>>> + g-rx-fifo-size = <768>;
>>>> + g-np-tx-fifo-size = <256>;
>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> };
>>>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>> index b05dac3ae308..4831350efdf2 100644
>>>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>> @@ -52,13 +52,38 @@
>>>> };
>>>>
>>>> cgu: x1830-cgu@10000000 {
>>>> - compatible = "ingenic,x1830-cgu";
>>>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>>>> reg = <0x10000000 0x100>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>
>>>> #clock-cells = <1>;
>>>>
>>>> clocks = <&exclk>, <&rtclk>;
>>>> clock-names = "ext", "rtc";
>>>> +
>>>> + otg_phy: usb-phy@3c {
>>>> + compatible = "ingenic,x1830-phy";
>>>> + reg = <0x3c 0x10>;
>>>> +
>>>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>>>> +
>>>> + #phy-cells = <0>;
>>>> + };
>>>> + };
>>>> +
>>>> + ost: timer@12000000 {
>>>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>>>> + reg = <0x12000000 0x3c>;
>>>> +
>>>> + #clock-cells = <1>;
>>>> +
>>>> + clocks = <&cgu X1830_CLK_OST>;
>>>> + clock-names = "ost";
>>>> +
>>>> + interrupt-parent = <&cpuintc>;
>>>> + interrupts = <4>;
>>>> };
>>>>
>>>> tcu: timer@10002000 {
>>>> @@ -236,6 +261,13 @@
>>>> status = "disabled";
>>>> };
>>>>
>>>> + dtrng: trng@10072000 {
>>>> + compatible = "ingenic,x1830-dtrng";
>>>> + reg = <0x10072000 0xc>;
>>>> +
>>>> + clocks = <&cgu X1830_CLK_DTRNG>;
>>>> + };
>>>> +
>>>> pdma: dma-controller@13420000 {
>>>> compatible = "ingenic,x1830-dma";
>>>> reg = <0x13420000 0x400
>>>> @@ -311,4 +343,24 @@
>>>> status = "disabled";
>>>> };
>>>> };
>>>> +
>>>> + otg: usb@13500000 {
>>>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>>>> + reg = <0x13500000 0x40000>;
>>>> +
>>>> + interrupt-parent = <&intc>;
>>>> + interrupts = <21>;
>>>> +
>>>> + clocks = <&cgu X1830_CLK_OTG>;
>>>> + clock-names = "otg";
>>>> +
>>>> + phys = <&otg_phy>;
>>>> + phy-names = "usb2-phy";
>>>> +
>>>> + g-rx-fifo-size = <768>;
>>>> + g-np-tx-fifo-size = <256>;
>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> };
>>>> --
>>>> 2.11.0
>>>>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. [and discussion about jz4780 SMP/MMC/Ethernet]
2020-11-08 15:13 ` Zhou Yanjie
@ 2020-11-08 15:28 ` H. Nikolaus Schaller
2020-11-10 5:25 ` Zhou Yanjie
0 siblings, 1 reply; 16+ messages in thread
From: H. Nikolaus Schaller @ 2020-11-08 15:28 UTC (permalink / raw)
To: Zhou Yanjie
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
> Am 08.11.2020 um 16:13 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>
>
> On 2020/11/8 下午10:35, H. Nikolaus Schaller wrote:
>>> Am 08.11.2020 um 13:46 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>>>
>>> Hello Nikolaus,
>>>
>>> On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
>>>>> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>>>>>
>>>>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>>>>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>>>>> nodes for CU1000-Neo.
>>>>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>>>>> nodes for CU1830-Neo.
>>>>>
>>>>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>>>> Comments below for CI20 / jz4780 only.
>>>>
>>>> I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
>>>> Maybe the SMP hacks are in the way and I have to remove them first or try on top
>>>> of v5.9.y
>>>
>>> SMP is not available on the mainline now, so the previous SMP patch needs to be removed.
>> I have tried with CONFIG_SMP disabled and now I can boot my v5.10-rc2 (plus local patches).
>> And can confirm that the OTG port works.
>
>
> Nice to hear it.
>
>
>> (BTW: dm9000 defers probing forever but that is an unrelated issue).
>
>
> On my side , it will work normally after selecting CONFIG_JZ4780_EFUSE.
Seems to be related to some vcc-supply:
[ 14.383309] dm9000 16000000.dm9000: Looking up vcc-supply from device tree
[ 14.442598] ------------[ cut here ]------------
[ 14.442626] WARNING: CPU: 0 PID: 19 at drivers/regulator/core.c:2125 _regulator_put+0x4c/0x104
[ 14.442631] Modules linked in: ohci_platform ingenic_drm(+) gpio_keys gpio_ir_recv ohci_hcd ehci_platform dw_hdmi dwc2 roles ehci_hcd drm_kms_helper dm9000 mii rtc_pcf8563 syscopyarea sysfillrect sysimgblt fb_sys_fops drm drm_panel_orientation_quirks ipv6 autofs4
[ 14.442723] CPU: 0 PID: 19 Comm: kworker/0:1 Tainted: G W 5.10.0-rc2-letux-mips+ #3790
[ 14.442738] Workqueue: events deferred_probe_work_func
[ 14.442745] Stack : 83941bd4 80165d58 00000000 80b70000 80b70000 80aaf3dc 80adad20 00000009
[ 14.442775] 0000084d 80165da4 80b6ff37 83936978 80b70000 00000001 83941b98 f6d2dfd3
[ 14.442805] 00000000 00000000 80aaf3dc 0000000c 00000114 00000002 00000001 746e6576
[ 14.442833] 65642073 00005c11 0000000f 72726566 80b70000 00000000 80590ad0 80adad20
[ 14.442862] 00000009 0000084d 00000001 80cb0000 00000000 805f6a28 0012829f 001282df
[ 14.442891] ...
[ 14.442901] Call Trace:
[ 14.442918] [<8010912c>] show_stack+0x6c/0x12c
[ 14.442933] [<801229e4>] __warn+0xd4/0x108
[ 14.442943] [<80122aa0>] warn_slowpath_fmt+0x88/0xc8
[ 14.442953] [<80590ad0>] _regulator_put+0x4c/0x104
[ 14.442961] [<80590bb0>] regulator_put+0x28/0x40
[ 14.442998] [<805dac8c>] release_nodes+0x220/0x280
[ 14.443013] [<808b1488>] really_probe+0x344/0x464
[ 14.443022] [<805d612c>] driver_probe_device+0x1d8/0x224
[ 14.443038] [<805d3efc>] bus_for_each_drv+0x90/0xc8
[ 14.443047] [<805d5e5c>] __device_attach+0xc8/0x174
[ 14.443057] [<805d4e3c>] bus_probe_device+0x3c/0xb4
[ 14.443066] [<805d53d4>] deferred_probe_work_func+0x7c/0xb4
[ 14.443078] [<8013d574>] process_one_work+0x204/0x348
[ 14.443087] [<8013e028>] worker_thread+0x28c/0x3c0
[ 14.443101] [<80143ac8>] kthread+0x14c/0x154
[ 14.443111] [<80102c0c>] ret_from_kernel_thread+0x14/0x1c
[ 14.443119]
[ 14.443126] ---[ end trace 76225a8e653eb480 ]---
[ 14.443379] platform 16000000.dm9000: Driver dm9000 requests probe deferral
>
>
>>> The new SMP patch will take some time because it needs to ensure support for the new X2000 processor.
>> Ok, I see. It is a little sad since it works find until 5.9 but now is broken and means we
>> have to test v5.10ff with only one processor. Any hints what should be hacked to make it
>> work until a final solution becomes available in upstream?
>
>
> I can try to make a version that supports JZ4780 first, and I will send it to you when it is completed.
Would be nice!
>
>
>>>
>>> Thanks and best regards!
>> If you like you can add my
>>
>> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
>>
>> to this patch.
>
>
> Sure, I will add it to the next version.
>
>
> BTW, have you noticed the problem with the MMC of JZ4780? This was first discovered by Paul. After he told me, I also tested it. When MMC has a relatively heavy load, there will indeed be many error messages related to mmcblk, and it is often accompanied by file system damage.
Yes, I have seen spurious mmcblk warnings and sometimes the CI20 did hang with heavy debootstrap load. No file system corruption so far. I thought it may be my µSD card but did not try another one. Or thought that the SMP code is not stable and I have to wait for a mainline solution...
>
> In addition, when doing some heavy work (such as compiling docker locally),
> the following warning message will be accompanied (this problem also exists on X1830):
>
> [ 4361.724410] warn_alloc: 1 callbacks suppressed
> [ 4361.724427] go: page allocation failure: order:5, mode:0x40cc0(GFP_KERNEL|__GFP_COMP), nodemask=(null)
> [ 4361.740945] CPU: 0 PID: 6792 Comm: go Tainted: G W 5.10.0-rc1+ #3
> [ 4361.748407] Stack : 80960000 801686ec 00000000 80879d2c 00000000 00000001 00000400 801688f8
> [ 4361.756845] 00000000 00000000 00000000 810891ca 84405c54 00000001 84405be8 810891ca
> [ 4361.765281] 00000000 00000000 8086054c 00000003 00000001 84405abc 00000000 00001cf1
> [ 4361.773717] bff4ffd7 2c29ee2f 84405ab4 2e352020 808f0000 80000000 00000000 80860000
> [ 4361.782153] 00000000 00000840 00000027 00000001 00000000 80441e34 017f02df 017f031f
> [ 4361.790588] ...
> [ 4361.793064] Call Trace:
> [ 4361.795547] [<80108bd4>] show_stack+0x6c/0x12c
> [ 4361.800023] [<80677974>] dump_stack+0xa0/0xd0
> [ 4361.804406] [<801f9e30>] warn_alloc+0xa8/0x130
> [ 4361.808875] [<801fa7ac>] __alloc_pages_nodemask+0x8d4/0x908
> [ 4361.814476] [<802076bc>] ____cache_alloc+0x2b4/0x600
> [ 4361.819467] [<80207de8>] __kmalloc+0x90/0x120
> [ 4361.823854] [<80296c8c>] proc_sys_call_handler+0xe4/0x230
> [ 4361.829280] [<8021901c>] vfs_read+0x12c/0x19c
> [ 4361.833662] [<802192c0>] ksys_read+0x80/0xe0
> [ 4361.837960] [<80110fb8>] syscall_common+0x34/0x58
> [ 4361.842687]
> [ 4361.854888] Mem-Info:
> [ 4361.858734] active_anon:240 inactive_anon:11673 isolated_anon:0
> [ 4361.858734] active_file:104199 inactive_file:53064 isolated_file:0
> [ 4361.858734] unevictable:0 dirty:366 writeback:0
> [ 4361.858734] slab_reclaimable:15980 slab_unreclaimable:2599
> [ 4361.858734] mapped:9755 shmem:3251 pagetables:229 bounce:0
> [ 4361.858734] free:67531 free_pcp:71 free_cma:3073
> [ 4361.915078] Node 0 active_anon:960kB inactive_anon:46708kB active_file:416796kB inactive_file:212268kB unevictable:0kB isolated(anon):0kB isolated(file):0kB mapped:39024kB dirty:1476kB writeback:0kB shmem:13004kB writeback_tmp:0kB kernel_stack:600kB all_unreclaimable? no
> [ 4361.940604] Normal free:33244kB min:1956kB low:2444kB high:2932kB reserved_highatomic:0KB active_anon:0kB inactive_anon:156kB active_file:82176kB inactive_file:47128kB unevictable:0kB writepending:1228kB present:262144kB managed:239444kB mlocked:0kB pagetables:908kB bounce:0kB free_pcp:120kB local_pcp:120kB free_cma:12300kB
> [ 4361.940612] lowmem_reserve[]: 0 6144 0
> [ 4361.974937] HighMem free:236820kB min:512kB low:2116kB high:3720kB reserved_highatomic:0KB active_anon:960kB inactive_anon:46552kB active_file:334620kB inactive_file:165140kB unevictable:0kB writepending:248kB present:786432kB managed:786432kB mlocked:0kB pagetables:0kB bounce:0kB free_pcp:240kB local_pcp:240kB free_cma:0kB
> [ 4361.974944] lowmem_reserve[]: 0 0 0
> [ 4362.008189] Normal: 2127*4kB (UMEC) 1508*8kB (UMEC) 472*16kB (UMEC) 96*32kB (UMC) 12*64kB (C) 4*128kB (C) 1*256kB (C) 1*512kB (C) 0*1024kB 0*2048kB 0*4096kB = 33244kB
> [ 4362.024364] HighMem: 1441*4kB (UM) 5376*8kB (UM) 3637*16kB (UM) 1210*32kB (UM) 498*64kB (UM) 225*128kB (UM) 69*256kB (UM) 23*512kB (UM) 1*1024kB (M) 0*2048kB 0*4096kB = 236820kB
> [ 4362.041152] 160520 total pagecache pages
> [ 4362.045838] 0 pages in swap cache
> [ 4362.049187] Swap cache stats: add 0, delete 0, find 0/0
> [ 4362.055501] Free swap = 0kB
> [ 4362.058413] Total swap = 0kB
> [ 4362.061315] 262144 pages RAM
> [ 4362.065588] 196608 pages HighMem/MovableOnly
> [ 4362.069889] 5675 pages reserved
> [ 4362.074159] 8192 pages cma reserved
>
> Do you have any idea?
Unfortunately no... Just some vague thoughts: maybe a lock is missing? Or cache corruption?
But we should maybe open another discussion because it is beyond the scope of this patch.
BR and thanks,
Nikolaus
>
>
> Thanks and best regards!
>
>
>>>
>>>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>>>>> ---
>>>>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>>>>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
>>>>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
>>>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>>>>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
>>>>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
>>>>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>>>>
>>>>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>>>>> index 75f5bfbf2c37..b31054a41754 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>>>>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>>>>> @@ -93,6 +93,15 @@
>>>>> clock-frequency = <48000000>;
>>>>> };
>>>>>
>>>>> +&cgu {
>>>>> + /*
>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>> + * precision.
>>>>> + */
>>>>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>>>>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>>>>> +};
>>>>> +
>>>> ok
>>>>
>>>>> &mmc0 {
>>>>> status = "okay";
>>>>>
>>>>> @@ -396,6 +405,13 @@
>>>>> status = "okay";
>>>>> };
>>>>>
>>>>> +&otg {
>>>>> + status = "okay";
>>>>> +
>>>>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>>>>> + assigned-clock-rates = <48000000>;
>>>>> +};
>>>>> +
>>>> ok
>>>>
>>>>> &pinctrl {
>>>>> pins_uart0: uart0 {
>>>>> function = "uart0";
>>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>> index 22a1066d637b..44d47d12db12 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>> @@ -3,7 +3,7 @@
>>>>>
>>>>> #include "x1000.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>
>>>>> / {
>>>>> @@ -31,6 +31,18 @@
>>>>> };
>>>>> };
>>>>>
>>>>> + ssi: spi-gpio {
>>>>> + compatible = "spi-gpio";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + num-chipselects = <1>;
>>>>> +
>>>>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>>>>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>>>>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>>>>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>>>>> + };
>>>>> +
>>>>> wlan_pwrseq: msc1-pwrseq {
>>>>> compatible = "mmc-pwrseq-simple";
>>>>>
>>>>> @@ -43,13 +55,19 @@
>>>>> clock-frequency = <24000000>;
>>>>> };
>>>>>
>>>>> -&tcu {
>>>>> +&cgu {
>>>>> + /*
>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>> + * precision.
>>>>> + */
>>>>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>>>>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>>>>> +};
>>>>> +
>>>>> +&ost {
>>>>> /* 1500 kHz for the system timer and clocksource */
>>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>>> -
>>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>>> };
>>>>>
>>>>> &uart2 {
>>>>> @@ -59,6 +77,32 @@
>>>>> pinctrl-0 = <&pins_uart2>;
>>>>> };
>>>>>
>>>>> +&ssi {
>>>>> + status = "okay";
>>>>> +
>>>>> + spi-max-frequency = <50000000>;
>>>>> +
>>>>> + sc16is752: expander@0 {
>>>>> + compatible = "nxp,sc16is752";
>>>>> + reg = <0>; /* CE0 */
>>>>> + spi-max-frequency = <4000000>;
>>>>> +
>>>>> + clocks = <&exclk_sc16is752>;
>>>>> +
>>>>> + interrupt-parent = <&gpc>;
>>>>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>>>>> +
>>>>> + gpio-controller;
>>>>> + #gpio-cells = <2>;
>>>>> +
>>>>> + exclk_sc16is752: sc16is752 {
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <48000000>;
>>>>> + };
>>>>> + };
>>>>> +};
>>>>> +
>>>>> &i2c0 {
>>>>> status = "okay";
>>>>>
>>>>> @@ -135,6 +179,10 @@
>>>>> };
>>>>> };
>>>>>
>>>>> +&otg {
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> &pinctrl {
>>>>> pins_uart2: uart2 {
>>>>> function = "uart2";
>>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>> index 640f96c00d63..7a56e344e429 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>> @@ -3,7 +3,7 @@
>>>>>
>>>>> #include "x1830.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>
>>>>> / {
>>>>> @@ -31,6 +31,18 @@
>>>>> };
>>>>> };
>>>>>
>>>>> + ssi0: spi-gpio {
>>>>> + compatible = "spi-gpio";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + num-chipselects = <1>;
>>>>> +
>>>>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>>>>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>>>>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>>>>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>>>>> + };
>>>>> +
>>>>> wlan_pwrseq: msc1-pwrseq {
>>>>> compatible = "mmc-pwrseq-simple";
>>>>>
>>>>> @@ -43,13 +55,19 @@
>>>>> clock-frequency = <24000000>;
>>>>> };
>>>>>
>>>>> -&tcu {
>>>>> +&cgu {
>>>>> + /*
>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>> + * precision.
>>>>> + */
>>>>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>>>>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>>>>> +};
>>>>> +
>>>>> +&ost {
>>>>> /* 1500 kHz for the system timer and clocksource */
>>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>>> -
>>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>>> };
>>>>>
>>>>> &uart1 {
>>>>> @@ -59,6 +77,32 @@
>>>>> pinctrl-0 = <&pins_uart1>;
>>>>> };
>>>>>
>>>>> +&ssi0 {
>>>>> + status = "okay";
>>>>> +
>>>>> + spi-max-frequency = <50000000>;
>>>>> +
>>>>> + sc16is752: expander@0 {
>>>>> + compatible = "nxp,sc16is752";
>>>>> + reg = <0>; /* CE0 */
>>>>> + spi-max-frequency = <4000000>;
>>>>> +
>>>>> + clocks = <&exclk_sc16is752>;
>>>>> +
>>>>> + interrupt-parent = <&gpb>;
>>>>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>>>> +
>>>>> + gpio-controller;
>>>>> + #gpio-cells = <2>;
>>>>> +
>>>>> + exclk_sc16is752: sc16is752 {
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <48000000>;
>>>>> + };
>>>>> + };
>>>>> +};
>>>>> +
>>>>> &i2c0 {
>>>>> status = "okay";
>>>>>
>>>>> @@ -135,6 +179,10 @@
>>>>> };
>>>>> };
>>>>>
>>>>> +&otg {
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> &pinctrl {
>>>>> pins_uart1: uart1 {
>>>>> function = "uart1";
>>>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>> index dfb5a7e1bb21..8837147e5a84 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>> @@ -61,13 +61,30 @@
>>>>> };
>>>>>
>>>>> cgu: jz4780-cgu@10000000 {
>>>>> - compatible = "ingenic,jz4780-cgu";
>>>>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>>>>> reg = <0x10000000 0x100>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>> +
>>>>> + #clock-cells = <1>;
>>>>>
>>>>> clocks = <&ext>, <&rtc>;
>>>>> clock-names = "ext", "rtc";
>>>>>
>>>>> - #clock-cells = <1>;
>>>>> + otg_phy: usb-phy@3c {
>>>>> + compatible = "ingenic,jz4780-phy";
>>>>> + reg = <0x3c 0x10>;
>>>>> +
>>>>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>>>>> +
>>>>> + #phy-cells = <0>;
>>>>> + };
>>>>> +
>>>>> + rng: rng@d8 {
>>>>> + compatible = "ingenic,jz4780-rng";
>>>>> + reg = <0xd8 0x8>;
>>>>> + };
>>>>> };
>>>>>
>>>>> tcu: timer@10002000 {
>>>>> @@ -494,4 +511,24 @@
>>>>>
>>>>> status = "disabled";
>>>>> };
>>>>> +
>>>>> + otg: usb@13500000 {
>>>>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>>>>> + reg = <0x13500000 0x40000>;
>>>>> +
>>>>> + interrupt-parent = <&intc>;
>>>>> + interrupts = <21>;
>>>>> +
>>>>> + clocks = <&cgu JZ4780_CLK_UHC>;
>>>>> + clock-names = "otg";
>>>>> +
>>>>> + phys = <&otg_phy>;
>>>>> + phy-names = "usb2-phy";
>>>>> +
>>>>> + g-rx-fifo-size = <768>;
>>>> I had tested with 256 before and do not see a reason why 768 should not work as well.
>>>>
>>>>> + g-np-tx-fifo-size = <256>;
>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>> +
>>>>> + status = "disabled";
>>>>> + };
>>>>> };
>>>>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>> index 1f1f896dd1f7..854fac58f45e 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>> @@ -52,13 +52,43 @@
>>>>> };
>>>>>
>>>>> cgu: x1000-cgu@10000000 {
>>>>> - compatible = "ingenic,x1000-cgu";
>>>>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>>>>> reg = <0x10000000 0x100>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>>
>>>>> #clock-cells = <1>;
>>>>>
>>>>> clocks = <&exclk>, <&rtclk>;
>>>>> clock-names = "ext", "rtc";
>>>>> +
>>>>> + otg_phy: usb-phy@3c {
>>>>> + compatible = "ingenic,x1000-phy";
>>>>> + reg = <0x3c 0x10>;
>>>>> +
>>>>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>>>>> +
>>>>> + #phy-cells = <0>;
>>>>> + };
>>>>> +
>>>>> + rng: rng@d8 {
>>>>> + compatible = "ingenic,x1000-rng";
>>>>> + reg = <0xd8 0x8>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + ost: timer@12000000 {
>>>>> + compatible = "ingenic,x1000-ost";
>>>>> + reg = <0x12000000 0x3c>;
>>>>> +
>>>>> + #clock-cells = <1>;
>>>>> +
>>>>> + clocks = <&cgu X1000_CLK_OST>;
>>>>> + clock-names = "ost";
>>>>> +
>>>>> + interrupt-parent = <&cpuintc>;
>>>>> + interrupts = <3>;
>>>>> };
>>>>>
>>>>> tcu: timer@10002000 {
>>>>> @@ -323,4 +353,24 @@
>>>>> status = "disabled";
>>>>> };
>>>>> };
>>>>> +
>>>>> + otg: usb@13500000 {
>>>>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>>>>> + reg = <0x13500000 0x40000>;
>>>>> +
>>>>> + interrupt-parent = <&intc>;
>>>>> + interrupts = <21>;
>>>>> +
>>>>> + clocks = <&cgu X1000_CLK_OTG>;
>>>>> + clock-names = "otg";
>>>>> +
>>>>> + phys = <&otg_phy>;
>>>>> + phy-names = "usb2-phy";
>>>>> +
>>>>> + g-rx-fifo-size = <768>;
>>>>> + g-np-tx-fifo-size = <256>;
>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>> +
>>>>> + status = "disabled";
>>>>> + };
>>>>> };
>>>>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>> index b05dac3ae308..4831350efdf2 100644
>>>>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>> @@ -52,13 +52,38 @@
>>>>> };
>>>>>
>>>>> cgu: x1830-cgu@10000000 {
>>>>> - compatible = "ingenic,x1830-cgu";
>>>>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>>>>> reg = <0x10000000 0x100>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>>
>>>>> #clock-cells = <1>;
>>>>>
>>>>> clocks = <&exclk>, <&rtclk>;
>>>>> clock-names = "ext", "rtc";
>>>>> +
>>>>> + otg_phy: usb-phy@3c {
>>>>> + compatible = "ingenic,x1830-phy";
>>>>> + reg = <0x3c 0x10>;
>>>>> +
>>>>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>>>>> +
>>>>> + #phy-cells = <0>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + ost: timer@12000000 {
>>>>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>>>>> + reg = <0x12000000 0x3c>;
>>>>> +
>>>>> + #clock-cells = <1>;
>>>>> +
>>>>> + clocks = <&cgu X1830_CLK_OST>;
>>>>> + clock-names = "ost";
>>>>> +
>>>>> + interrupt-parent = <&cpuintc>;
>>>>> + interrupts = <4>;
>>>>> };
>>>>>
>>>>> tcu: timer@10002000 {
>>>>> @@ -236,6 +261,13 @@
>>>>> status = "disabled";
>>>>> };
>>>>>
>>>>> + dtrng: trng@10072000 {
>>>>> + compatible = "ingenic,x1830-dtrng";
>>>>> + reg = <0x10072000 0xc>;
>>>>> +
>>>>> + clocks = <&cgu X1830_CLK_DTRNG>;
>>>>> + };
>>>>> +
>>>>> pdma: dma-controller@13420000 {
>>>>> compatible = "ingenic,x1830-dma";
>>>>> reg = <0x13420000 0x400
>>>>> @@ -311,4 +343,24 @@
>>>>> status = "disabled";
>>>>> };
>>>>> };
>>>>> +
>>>>> + otg: usb@13500000 {
>>>>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>>>>> + reg = <0x13500000 0x40000>;
>>>>> +
>>>>> + interrupt-parent = <&intc>;
>>>>> + interrupts = <21>;
>>>>> +
>>>>> + clocks = <&cgu X1830_CLK_OTG>;
>>>>> + clock-names = "otg";
>>>>> +
>>>>> + phys = <&otg_phy>;
>>>>> + phy-names = "usb2-phy";
>>>>> +
>>>>> + g-rx-fifo-size = <768>;
>>>>> + g-np-tx-fifo-size = <256>;
>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>> +
>>>>> + status = "disabled";
>>>>> + };
>>>>> };
>>>>> --
>>>>> 2.11.0
>>>>>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. [and discussion about jz4780 SMP/MMC/Ethernet]
2020-11-08 15:28 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. [and discussion about jz4780 SMP/MMC/Ethernet] H. Nikolaus Schaller
@ 2020-11-10 5:25 ` Zhou Yanjie
0 siblings, 0 replies; 16+ messages in thread
From: Zhou Yanjie @ 2020-11-10 5:25 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: tsbogend, paul, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
On 2020/11/8 下午11:28, H. Nikolaus Schaller wrote:
>> Am 08.11.2020 um 16:13 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>>
>>
>> On 2020/11/8 下午10:35, H. Nikolaus Schaller wrote:
>>>> Am 08.11.2020 um 13:46 schrieb Zhou Yanjie <zhouyanjie@wanyeetech.com>:
>>>>
>>>> Hello Nikolaus,
>>>>
>>>> On 2020/11/8 上午3:03, H. Nikolaus Schaller wrote:
>>>>>> Am 07.11.2020 um 12:52 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>>>>>>
>>>>>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>>>>>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>>>>>> nodes for CU1000-Neo.
>>>>>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>>>>>> nodes for CU1830-Neo.
>>>>>>
>>>>>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>>>>> Comments below for CI20 / jz4780 only.
>>>>>
>>>>> I tried to test on top of my v5.10 working tree but the CI20 does not boot any more.
>>>>> Maybe the SMP hacks are in the way and I have to remove them first or try on top
>>>>> of v5.9.y
>>>> SMP is not available on the mainline now, so the previous SMP patch needs to be removed.
>>> I have tried with CONFIG_SMP disabled and now I can boot my v5.10-rc2 (plus local patches).
>>> And can confirm that the OTG port works.
>>
>> Nice to hear it.
>>
>>
>>> (BTW: dm9000 defers probing forever but that is an unrelated issue).
>>
>> On my side , it will work normally after selecting CONFIG_JZ4780_EFUSE.
> Seems to be related to some vcc-supply:
>
> [ 14.383309] dm9000 16000000.dm9000: Looking up vcc-supply from device tree
> [ 14.442598] ------------[ cut here ]------------
> [ 14.442626] WARNING: CPU: 0 PID: 19 at drivers/regulator/core.c:2125 _regulator_put+0x4c/0x104
> [ 14.442631] Modules linked in: ohci_platform ingenic_drm(+) gpio_keys gpio_ir_recv ohci_hcd ehci_platform dw_hdmi dwc2 roles ehci_hcd drm_kms_helper dm9000 mii rtc_pcf8563 syscopyarea sysfillrect sysimgblt fb_sys_fops drm drm_panel_orientation_quirks ipv6 autofs4
> [ 14.442723] CPU: 0 PID: 19 Comm: kworker/0:1 Tainted: G W 5.10.0-rc2-letux-mips+ #3790
> [ 14.442738] Workqueue: events deferred_probe_work_func
> [ 14.442745] Stack : 83941bd4 80165d58 00000000 80b70000 80b70000 80aaf3dc 80adad20 00000009
> [ 14.442775] 0000084d 80165da4 80b6ff37 83936978 80b70000 00000001 83941b98 f6d2dfd3
> [ 14.442805] 00000000 00000000 80aaf3dc 0000000c 00000114 00000002 00000001 746e6576
> [ 14.442833] 65642073 00005c11 0000000f 72726566 80b70000 00000000 80590ad0 80adad20
> [ 14.442862] 00000009 0000084d 00000001 80cb0000 00000000 805f6a28 0012829f 001282df
> [ 14.442891] ...
> [ 14.442901] Call Trace:
> [ 14.442918] [<8010912c>] show_stack+0x6c/0x12c
> [ 14.442933] [<801229e4>] __warn+0xd4/0x108
> [ 14.442943] [<80122aa0>] warn_slowpath_fmt+0x88/0xc8
> [ 14.442953] [<80590ad0>] _regulator_put+0x4c/0x104
> [ 14.442961] [<80590bb0>] regulator_put+0x28/0x40
> [ 14.442998] [<805dac8c>] release_nodes+0x220/0x280
> [ 14.443013] [<808b1488>] really_probe+0x344/0x464
> [ 14.443022] [<805d612c>] driver_probe_device+0x1d8/0x224
> [ 14.443038] [<805d3efc>] bus_for_each_drv+0x90/0xc8
> [ 14.443047] [<805d5e5c>] __device_attach+0xc8/0x174
> [ 14.443057] [<805d4e3c>] bus_probe_device+0x3c/0xb4
> [ 14.443066] [<805d53d4>] deferred_probe_work_func+0x7c/0xb4
> [ 14.443078] [<8013d574>] process_one_work+0x204/0x348
> [ 14.443087] [<8013e028>] worker_thread+0x28c/0x3c0
> [ 14.443101] [<80143ac8>] kthread+0x14c/0x154
> [ 14.443111] [<80102c0c>] ret_from_kernel_thread+0x14/0x1c
> [ 14.443119]
> [ 14.443126] ---[ end trace 76225a8e653eb480 ]---
> [ 14.443379] platform 16000000.dm9000: Driver dm9000 requests probe deferral
>
I also reproduce this phenomenon here, but no idea yet.
>>
>>>> The new SMP patch will take some time because it needs to ensure support for the new X2000 processor.
>>> Ok, I see. It is a little sad since it works find until 5.9 but now is broken and means we
>>> have to test v5.10ff with only one processor. Any hints what should be hacked to make it
>>> work until a final solution becomes available in upstream?
>>
>> I can try to make a version that supports JZ4780 first, and I will send it to you when it is completed.
> Would be nice!
>
I have completed a version and will send it to you later.
>>
>>>> Thanks and best regards!
>>> If you like you can add my
>>>
>>> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
>>>
>>> to this patch.
>>
>> Sure, I will add it to the next version.
>>
>>
>> BTW, have you noticed the problem with the MMC of JZ4780? This was first discovered by Paul. After he told me, I also tested it. When MMC has a relatively heavy load, there will indeed be many error messages related to mmcblk, and it is often accompanied by file system damage.
> Yes, I have seen spurious mmcblk warnings and sometimes the CI20 did hang with heavy debootstrap load. No file system corruption so far. I thought it may be my µSD card but did not try another one. Or thought that the SMP code is not stable and I have to wait for a mainline solution...
>
It seems to be related to the working frequency, and it seems to be
related to the cache and mmc drivers, I am studying this issue.
>> In addition, when doing some heavy work (such as compiling docker locally),
>> the following warning message will be accompanied (this problem also exists on X1830):
>>
>> [ 4361.724410] warn_alloc: 1 callbacks suppressed
>> [ 4361.724427] go: page allocation failure: order:5, mode:0x40cc0(GFP_KERNEL|__GFP_COMP), nodemask=(null)
>> [ 4361.740945] CPU: 0 PID: 6792 Comm: go Tainted: G W 5.10.0-rc1+ #3
>> [ 4361.748407] Stack : 80960000 801686ec 00000000 80879d2c 00000000 00000001 00000400 801688f8
>> [ 4361.756845] 00000000 00000000 00000000 810891ca 84405c54 00000001 84405be8 810891ca
>> [ 4361.765281] 00000000 00000000 8086054c 00000003 00000001 84405abc 00000000 00001cf1
>> [ 4361.773717] bff4ffd7 2c29ee2f 84405ab4 2e352020 808f0000 80000000 00000000 80860000
>> [ 4361.782153] 00000000 00000840 00000027 00000001 00000000 80441e34 017f02df 017f031f
>> [ 4361.790588] ...
>> [ 4361.793064] Call Trace:
>> [ 4361.795547] [<80108bd4>] show_stack+0x6c/0x12c
>> [ 4361.800023] [<80677974>] dump_stack+0xa0/0xd0
>> [ 4361.804406] [<801f9e30>] warn_alloc+0xa8/0x130
>> [ 4361.808875] [<801fa7ac>] __alloc_pages_nodemask+0x8d4/0x908
>> [ 4361.814476] [<802076bc>] ____cache_alloc+0x2b4/0x600
>> [ 4361.819467] [<80207de8>] __kmalloc+0x90/0x120
>> [ 4361.823854] [<80296c8c>] proc_sys_call_handler+0xe4/0x230
>> [ 4361.829280] [<8021901c>] vfs_read+0x12c/0x19c
>> [ 4361.833662] [<802192c0>] ksys_read+0x80/0xe0
>> [ 4361.837960] [<80110fb8>] syscall_common+0x34/0x58
>> [ 4361.842687]
>> [ 4361.854888] Mem-Info:
>> [ 4361.858734] active_anon:240 inactive_anon:11673 isolated_anon:0
>> [ 4361.858734] active_file:104199 inactive_file:53064 isolated_file:0
>> [ 4361.858734] unevictable:0 dirty:366 writeback:0
>> [ 4361.858734] slab_reclaimable:15980 slab_unreclaimable:2599
>> [ 4361.858734] mapped:9755 shmem:3251 pagetables:229 bounce:0
>> [ 4361.858734] free:67531 free_pcp:71 free_cma:3073
>> [ 4361.915078] Node 0 active_anon:960kB inactive_anon:46708kB active_file:416796kB inactive_file:212268kB unevictable:0kB isolated(anon):0kB isolated(file):0kB mapped:39024kB dirty:1476kB writeback:0kB shmem:13004kB writeback_tmp:0kB kernel_stack:600kB all_unreclaimable? no
>> [ 4361.940604] Normal free:33244kB min:1956kB low:2444kB high:2932kB reserved_highatomic:0KB active_anon:0kB inactive_anon:156kB active_file:82176kB inactive_file:47128kB unevictable:0kB writepending:1228kB present:262144kB managed:239444kB mlocked:0kB pagetables:908kB bounce:0kB free_pcp:120kB local_pcp:120kB free_cma:12300kB
>> [ 4361.940612] lowmem_reserve[]: 0 6144 0
>> [ 4361.974937] HighMem free:236820kB min:512kB low:2116kB high:3720kB reserved_highatomic:0KB active_anon:960kB inactive_anon:46552kB active_file:334620kB inactive_file:165140kB unevictable:0kB writepending:248kB present:786432kB managed:786432kB mlocked:0kB pagetables:0kB bounce:0kB free_pcp:240kB local_pcp:240kB free_cma:0kB
>> [ 4361.974944] lowmem_reserve[]: 0 0 0
>> [ 4362.008189] Normal: 2127*4kB (UMEC) 1508*8kB (UMEC) 472*16kB (UMEC) 96*32kB (UMC) 12*64kB (C) 4*128kB (C) 1*256kB (C) 1*512kB (C) 0*1024kB 0*2048kB 0*4096kB = 33244kB
>> [ 4362.024364] HighMem: 1441*4kB (UM) 5376*8kB (UM) 3637*16kB (UM) 1210*32kB (UM) 498*64kB (UM) 225*128kB (UM) 69*256kB (UM) 23*512kB (UM) 1*1024kB (M) 0*2048kB 0*4096kB = 236820kB
>> [ 4362.041152] 160520 total pagecache pages
>> [ 4362.045838] 0 pages in swap cache
>> [ 4362.049187] Swap cache stats: add 0, delete 0, find 0/0
>> [ 4362.055501] Free swap = 0kB
>> [ 4362.058413] Total swap = 0kB
>> [ 4362.061315] 262144 pages RAM
>> [ 4362.065588] 196608 pages HighMem/MovableOnly
>> [ 4362.069889] 5675 pages reserved
>> [ 4362.074159] 8192 pages cma reserved
>>
>> Do you have any idea?
> Unfortunately no... Just some vague thoughts: maybe a lock is missing? Or cache corruption?
>
> But we should maybe open another discussion because it is beyond the scope of this patch.
Sure.
Thanks and best regards!
> BR and thanks,
> Nikolaus
>
>>
>> Thanks and best regards!
>>
>>
>>>>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>>>>>> ---
>>>>>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>>>>>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60 +++++++++++++++++++++++++++----
>>>>>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60 +++++++++++++++++++++++++++----
>>>>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>>>>>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52 ++++++++++++++++++++++++++-
>>>>>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54 +++++++++++++++++++++++++++-
>>>>>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>>>>>> index 75f5bfbf2c37..b31054a41754 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>>>>>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>>>>>> @@ -93,6 +93,15 @@
>>>>>> clock-frequency = <48000000>;
>>>>>> };
>>>>>>
>>>>>> +&cgu {
>>>>>> + /*
>>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>>> + * precision.
>>>>>> + */
>>>>>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>>>>>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>>>>>> +};
>>>>>> +
>>>>> ok
>>>>>
>>>>>> &mmc0 {
>>>>>> status = "okay";
>>>>>>
>>>>>> @@ -396,6 +405,13 @@
>>>>>> status = "okay";
>>>>>> };
>>>>>>
>>>>>> +&otg {
>>>>>> + status = "okay";
>>>>>> +
>>>>>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>>>>>> + assigned-clock-rates = <48000000>;
>>>>>> +};
>>>>>> +
>>>>> ok
>>>>>
>>>>>> &pinctrl {
>>>>>> pins_uart0: uart0 {
>>>>>> function = "uart0";
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>>> index 22a1066d637b..44d47d12db12 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>>>>> @@ -3,7 +3,7 @@
>>>>>>
>>>>>> #include "x1000.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>
>>>>>> / {
>>>>>> @@ -31,6 +31,18 @@
>>>>>> };
>>>>>> };
>>>>>>
>>>>>> + ssi: spi-gpio {
>>>>>> + compatible = "spi-gpio";
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <0>;
>>>>>> + num-chipselects = <1>;
>>>>>> +
>>>>>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>>>>>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>>>>>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>>>>>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>>>>>> + };
>>>>>> +
>>>>>> wlan_pwrseq: msc1-pwrseq {
>>>>>> compatible = "mmc-pwrseq-simple";
>>>>>>
>>>>>> @@ -43,13 +55,19 @@
>>>>>> clock-frequency = <24000000>;
>>>>>> };
>>>>>>
>>>>>> -&tcu {
>>>>>> +&cgu {
>>>>>> + /*
>>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>>> + * precision.
>>>>>> + */
>>>>>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>>>>>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>>>>>> +};
>>>>>> +
>>>>>> +&ost {
>>>>>> /* 1500 kHz for the system timer and clocksource */
>>>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>>>> -
>>>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>>>> };
>>>>>>
>>>>>> &uart2 {
>>>>>> @@ -59,6 +77,32 @@
>>>>>> pinctrl-0 = <&pins_uart2>;
>>>>>> };
>>>>>>
>>>>>> +&ssi {
>>>>>> + status = "okay";
>>>>>> +
>>>>>> + spi-max-frequency = <50000000>;
>>>>>> +
>>>>>> + sc16is752: expander@0 {
>>>>>> + compatible = "nxp,sc16is752";
>>>>>> + reg = <0>; /* CE0 */
>>>>>> + spi-max-frequency = <4000000>;
>>>>>> +
>>>>>> + clocks = <&exclk_sc16is752>;
>>>>>> +
>>>>>> + interrupt-parent = <&gpc>;
>>>>>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>>>>>> +
>>>>>> + gpio-controller;
>>>>>> + #gpio-cells = <2>;
>>>>>> +
>>>>>> + exclk_sc16is752: sc16is752 {
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <48000000>;
>>>>>> + };
>>>>>> + };
>>>>>> +};
>>>>>> +
>>>>>> &i2c0 {
>>>>>> status = "okay";
>>>>>>
>>>>>> @@ -135,6 +179,10 @@
>>>>>> };
>>>>>> };
>>>>>>
>>>>>> +&otg {
>>>>>> + status = "okay";
>>>>>> +};
>>>>>> +
>>>>>> &pinctrl {
>>>>>> pins_uart2: uart2 {
>>>>>> function = "uart2";
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>>> index 640f96c00d63..7a56e344e429 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>>>>> @@ -3,7 +3,7 @@
>>>>>>
>>>>>> #include "x1830.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>>>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>
>>>>>> / {
>>>>>> @@ -31,6 +31,18 @@
>>>>>> };
>>>>>> };
>>>>>>
>>>>>> + ssi0: spi-gpio {
>>>>>> + compatible = "spi-gpio";
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <0>;
>>>>>> + num-chipselects = <1>;
>>>>>> +
>>>>>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>>>>>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>>>>>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>>>>>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>>>>>> + };
>>>>>> +
>>>>>> wlan_pwrseq: msc1-pwrseq {
>>>>>> compatible = "mmc-pwrseq-simple";
>>>>>>
>>>>>> @@ -43,13 +55,19 @@
>>>>>> clock-frequency = <24000000>;
>>>>>> };
>>>>>>
>>>>>> -&tcu {
>>>>>> +&cgu {
>>>>>> + /*
>>>>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
>>>>>> + * precision.
>>>>>> + */
>>>>>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>>>>>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>>>>>> +};
>>>>>> +
>>>>>> +&ost {
>>>>>> /* 1500 kHz for the system timer and clocksource */
>>>>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>>>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
>>>>>> assigned-clock-rates = <1500000>, <1500000>;
>>>>>> -
>>>>>> - /* Use channel #0 for the system timer channel #2 for the clocksource */
>>>>>> - ingenic,pwm-channels-mask = <0xfa>;
>>>>>> };
>>>>>>
>>>>>> &uart1 {
>>>>>> @@ -59,6 +77,32 @@
>>>>>> pinctrl-0 = <&pins_uart1>;
>>>>>> };
>>>>>>
>>>>>> +&ssi0 {
>>>>>> + status = "okay";
>>>>>> +
>>>>>> + spi-max-frequency = <50000000>;
>>>>>> +
>>>>>> + sc16is752: expander@0 {
>>>>>> + compatible = "nxp,sc16is752";
>>>>>> + reg = <0>; /* CE0 */
>>>>>> + spi-max-frequency = <4000000>;
>>>>>> +
>>>>>> + clocks = <&exclk_sc16is752>;
>>>>>> +
>>>>>> + interrupt-parent = <&gpb>;
>>>>>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>>>>> +
>>>>>> + gpio-controller;
>>>>>> + #gpio-cells = <2>;
>>>>>> +
>>>>>> + exclk_sc16is752: sc16is752 {
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <48000000>;
>>>>>> + };
>>>>>> + };
>>>>>> +};
>>>>>> +
>>>>>> &i2c0 {
>>>>>> status = "okay";
>>>>>>
>>>>>> @@ -135,6 +179,10 @@
>>>>>> };
>>>>>> };
>>>>>>
>>>>>> +&otg {
>>>>>> + status = "okay";
>>>>>> +};
>>>>>> +
>>>>>> &pinctrl {
>>>>>> pins_uart1: uart1 {
>>>>>> function = "uart1";
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>>> index dfb5a7e1bb21..8837147e5a84 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>>>>> @@ -61,13 +61,30 @@
>>>>>> };
>>>>>>
>>>>>> cgu: jz4780-cgu@10000000 {
>>>>>> - compatible = "ingenic,jz4780-cgu";
>>>>>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>>>>>> reg = <0x10000000 0x100>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>>> +
>>>>>> + #clock-cells = <1>;
>>>>>>
>>>>>> clocks = <&ext>, <&rtc>;
>>>>>> clock-names = "ext", "rtc";
>>>>>>
>>>>>> - #clock-cells = <1>;
>>>>>> + otg_phy: usb-phy@3c {
>>>>>> + compatible = "ingenic,jz4780-phy";
>>>>>> + reg = <0x3c 0x10>;
>>>>>> +
>>>>>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>>>>>> +
>>>>>> + #phy-cells = <0>;
>>>>>> + };
>>>>>> +
>>>>>> + rng: rng@d8 {
>>>>>> + compatible = "ingenic,jz4780-rng";
>>>>>> + reg = <0xd8 0x8>;
>>>>>> + };
>>>>>> };
>>>>>>
>>>>>> tcu: timer@10002000 {
>>>>>> @@ -494,4 +511,24 @@
>>>>>>
>>>>>> status = "disabled";
>>>>>> };
>>>>>> +
>>>>>> + otg: usb@13500000 {
>>>>>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>>>>>> + reg = <0x13500000 0x40000>;
>>>>>> +
>>>>>> + interrupt-parent = <&intc>;
>>>>>> + interrupts = <21>;
>>>>>> +
>>>>>> + clocks = <&cgu JZ4780_CLK_UHC>;
>>>>>> + clock-names = "otg";
>>>>>> +
>>>>>> + phys = <&otg_phy>;
>>>>>> + phy-names = "usb2-phy";
>>>>>> +
>>>>>> + g-rx-fifo-size = <768>;
>>>>> I had tested with 256 before and do not see a reason why 768 should not work as well.
>>>>>
>>>>>> + g-np-tx-fifo-size = <256>;
>>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>>> +
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> };
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>>> index 1f1f896dd1f7..854fac58f45e 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>>>>> @@ -52,13 +52,43 @@
>>>>>> };
>>>>>>
>>>>>> cgu: x1000-cgu@10000000 {
>>>>>> - compatible = "ingenic,x1000-cgu";
>>>>>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>>>>>> reg = <0x10000000 0x100>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>>>
>>>>>> #clock-cells = <1>;
>>>>>>
>>>>>> clocks = <&exclk>, <&rtclk>;
>>>>>> clock-names = "ext", "rtc";
>>>>>> +
>>>>>> + otg_phy: usb-phy@3c {
>>>>>> + compatible = "ingenic,x1000-phy";
>>>>>> + reg = <0x3c 0x10>;
>>>>>> +
>>>>>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>>>>>> +
>>>>>> + #phy-cells = <0>;
>>>>>> + };
>>>>>> +
>>>>>> + rng: rng@d8 {
>>>>>> + compatible = "ingenic,x1000-rng";
>>>>>> + reg = <0xd8 0x8>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + ost: timer@12000000 {
>>>>>> + compatible = "ingenic,x1000-ost";
>>>>>> + reg = <0x12000000 0x3c>;
>>>>>> +
>>>>>> + #clock-cells = <1>;
>>>>>> +
>>>>>> + clocks = <&cgu X1000_CLK_OST>;
>>>>>> + clock-names = "ost";
>>>>>> +
>>>>>> + interrupt-parent = <&cpuintc>;
>>>>>> + interrupts = <3>;
>>>>>> };
>>>>>>
>>>>>> tcu: timer@10002000 {
>>>>>> @@ -323,4 +353,24 @@
>>>>>> status = "disabled";
>>>>>> };
>>>>>> };
>>>>>> +
>>>>>> + otg: usb@13500000 {
>>>>>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>>>>>> + reg = <0x13500000 0x40000>;
>>>>>> +
>>>>>> + interrupt-parent = <&intc>;
>>>>>> + interrupts = <21>;
>>>>>> +
>>>>>> + clocks = <&cgu X1000_CLK_OTG>;
>>>>>> + clock-names = "otg";
>>>>>> +
>>>>>> + phys = <&otg_phy>;
>>>>>> + phy-names = "usb2-phy";
>>>>>> +
>>>>>> + g-rx-fifo-size = <768>;
>>>>>> + g-np-tx-fifo-size = <256>;
>>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>>> +
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> };
>>>>>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>>> index b05dac3ae308..4831350efdf2 100644
>>>>>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>>>>> @@ -52,13 +52,38 @@
>>>>>> };
>>>>>>
>>>>>> cgu: x1830-cgu@10000000 {
>>>>>> - compatible = "ingenic,x1830-cgu";
>>>>>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>>>>>> reg = <0x10000000 0x100>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>> + ranges = <0x0 0x10000000 0x100>;
>>>>>>
>>>>>> #clock-cells = <1>;
>>>>>>
>>>>>> clocks = <&exclk>, <&rtclk>;
>>>>>> clock-names = "ext", "rtc";
>>>>>> +
>>>>>> + otg_phy: usb-phy@3c {
>>>>>> + compatible = "ingenic,x1830-phy";
>>>>>> + reg = <0x3c 0x10>;
>>>>>> +
>>>>>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>>>>>> +
>>>>>> + #phy-cells = <0>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + ost: timer@12000000 {
>>>>>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>>>>>> + reg = <0x12000000 0x3c>;
>>>>>> +
>>>>>> + #clock-cells = <1>;
>>>>>> +
>>>>>> + clocks = <&cgu X1830_CLK_OST>;
>>>>>> + clock-names = "ost";
>>>>>> +
>>>>>> + interrupt-parent = <&cpuintc>;
>>>>>> + interrupts = <4>;
>>>>>> };
>>>>>>
>>>>>> tcu: timer@10002000 {
>>>>>> @@ -236,6 +261,13 @@
>>>>>> status = "disabled";
>>>>>> };
>>>>>>
>>>>>> + dtrng: trng@10072000 {
>>>>>> + compatible = "ingenic,x1830-dtrng";
>>>>>> + reg = <0x10072000 0xc>;
>>>>>> +
>>>>>> + clocks = <&cgu X1830_CLK_DTRNG>;
>>>>>> + };
>>>>>> +
>>>>>> pdma: dma-controller@13420000 {
>>>>>> compatible = "ingenic,x1830-dma";
>>>>>> reg = <0x13420000 0x400
>>>>>> @@ -311,4 +343,24 @@
>>>>>> status = "disabled";
>>>>>> };
>>>>>> };
>>>>>> +
>>>>>> + otg: usb@13500000 {
>>>>>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>>>>>> + reg = <0x13500000 0x40000>;
>>>>>> +
>>>>>> + interrupt-parent = <&intc>;
>>>>>> + interrupts = <21>;
>>>>>> +
>>>>>> + clocks = <&cgu X1830_CLK_OTG>;
>>>>>> + clock-names = "otg";
>>>>>> +
>>>>>> + phys = <&otg_phy>;
>>>>>> + phy-names = "usb2-phy";
>>>>>> +
>>>>>> + g-rx-fifo-size = <768>;
>>>>>> + g-np-tx-fifo-size = <256>;
>>>>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>>>>> +
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> };
>>>>>> --
>>>>>> 2.11.0
>>>>>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-07 11:52 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards 周琰杰 (Zhou Yanjie)
2020-11-07 19:03 ` H. Nikolaus Schaller
@ 2020-11-09 23:30 ` Paul Cercueil
2020-11-10 5:27 ` Zhou Yanjie
2020-11-09 23:37 ` Paul Cercueil
2 siblings, 1 reply; 16+ messages in thread
From: Paul Cercueil @ 2020-11-09 23:30 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, hns, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Hi Zhou,
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1000-Neo.
> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1830-Neo.
>
> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60
> +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60
> +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
> arch/mips/boot/dts/ingenic/x1000.dtsi | 52
> ++++++++++++++++++++++++++-
> arch/mips/boot/dts/ingenic/x1830.dtsi | 54
> +++++++++++++++++++++++++++-
> 6 files changed, 267 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 75f5bfbf2c37..b31054a41754 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -93,6 +93,15 @@
> clock-frequency = <48000000>;
> };
>
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
> +};
> +
> &mmc0 {
> status = "okay";
>
> @@ -396,6 +405,13 @@
> status = "okay";
> };
>
> +&otg {
> + status = "okay";
> +
> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
> + assigned-clock-rates = <48000000>;
I think you should put these two lines inside &cgu. While it will also
work here, the assigned-clocks / assigned-clock-rates are defined
Device Tree properties only for clock controller nodes, and so "make
dtbs_check" will complain:
ci20.dt.yaml: usb@13500000: 'assigned-clock-rates', 'assigned-clocks'
do not match any of the regexes: 'pinctrl-[0-9]+'
Same in the Neo .dts files.
> +};
> +
> &pinctrl {
> pins_uart0: uart0 {
> function = "uart0";
> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> index 22a1066d637b..44d47d12db12 100644
> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1000.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1000_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
> OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the
> clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart2 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart2>;
> };
>
> +&ssi {
"ssi" is defined right above, you can put the expander node and
properties directly there.
Cheers,
-Paul
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpc>;
> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart2: uart2 {
> function = "uart2";
> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> index 640f96c00d63..7a56e344e429 100644
> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1830.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi0: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1830_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
> OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the
> clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart1 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart1>;
> };
>
> +&ssi0 {
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpb>;
> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart1: uart1 {
> function = "uart1";
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index dfb5a7e1bb21..8837147e5a84 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -61,13 +61,30 @@
> };
>
> cgu: jz4780-cgu@10000000 {
> - compatible = "ingenic,jz4780-cgu";
> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
> +
> + #clock-cells = <1>;
>
> clocks = <&ext>, <&rtc>;
> clock-names = "ext", "rtc";
>
> - #clock-cells = <1>;
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,jz4780-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu JZ4780_CLK_OTG1>;
> +
> + #phy-cells = <0>;
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,jz4780-rng";
> + reg = <0xd8 0x8>;
> + };
> };
>
> tcu: timer@10002000 {
> @@ -494,4 +511,24 @@
>
> status = "disabled";
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu JZ4780_CLK_UHC>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index 1f1f896dd1f7..854fac58f45e 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -52,13 +52,43 @@
> };
>
> cgu: x1000-cgu@10000000 {
> - compatible = "ingenic,x1000-cgu";
> + compatible = "ingenic,x1000-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1000-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1000_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,x1000-rng";
> + reg = <0xd8 0x8>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1000_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <3>;
> };
>
> tcu: timer@10002000 {
> @@ -323,4 +353,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1000-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1000_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index b05dac3ae308..4831350efdf2 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -52,13 +52,38 @@
> };
>
> cgu: x1830-cgu@10000000 {
> - compatible = "ingenic,x1830-cgu";
> + compatible = "ingenic,x1830-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1830-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1830_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1830_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <4>;
> };
>
> tcu: timer@10002000 {
> @@ -236,6 +261,13 @@
> status = "disabled";
> };
>
> + dtrng: trng@10072000 {
> + compatible = "ingenic,x1830-dtrng";
> + reg = <0x10072000 0xc>;
> +
> + clocks = <&cgu X1830_CLK_DTRNG>;
> + };
> +
> pdma: dma-controller@13420000 {
> compatible = "ingenic,x1830-dma";
> reg = <0x13420000 0x400
> @@ -311,4 +343,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1830-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1830_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-09 23:30 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards Paul Cercueil
@ 2020-11-10 5:27 ` Zhou Yanjie
0 siblings, 0 replies; 16+ messages in thread
From: Zhou Yanjie @ 2020-11-10 5:27 UTC (permalink / raw)
To: Paul Cercueil
Cc: tsbogend, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, hns, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Hi Paul,
On 2020/11/10 上午7:30, Paul Cercueil wrote:
> Hi Zhou,
>
> Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1000-Neo.
>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1830-Neo.
>>
>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> ---
>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60
>> +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60
>> +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52
>> ++++++++++++++++++++++++++-
>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54
>> +++++++++++++++++++++++++++-
>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
>> b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 75f5bfbf2c37..b31054a41754 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -93,6 +93,15 @@
>> clock-frequency = <48000000>;
>> };
>>
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>> +};
>> +
>> &mmc0 {
>> status = "okay";
>>
>> @@ -396,6 +405,13 @@
>> status = "okay";
>> };
>>
>> +&otg {
>> + status = "okay";
>> +
>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>> + assigned-clock-rates = <48000000>;
>
> I think you should put these two lines inside &cgu. While it will also
> work here, the assigned-clocks / assigned-clock-rates are defined
> Device Tree properties only for clock controller nodes, and so "make
> dtbs_check" will complain:
>
> ci20.dt.yaml: usb@13500000: 'assigned-clock-rates', 'assigned-clocks'
> do not match any of the regexes: 'pinctrl-[0-9]+'
>
> Same in the Neo .dts files.
Sure, I will move it into CGU node in the next version.
>
>> +};
>> +
>> &pinctrl {
>> pins_uart0: uart0 {
>> function = "uart0";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> index 22a1066d637b..44d47d12db12 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1000.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>> OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the
>> clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart2 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart2>;
>> };
>>
>> +&ssi {
>
> "ssi" is defined right above, you can put the expander node and
> properties directly there.
>
Sure.
Thanks and best regards!
> Cheers,
> -Paul
>
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpc>;
>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart2: uart2 {
>> function = "uart2";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> index 640f96c00d63..7a56e344e429 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1830.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi0: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>> OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the
>> clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart1 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart1>;
>> };
>>
>> +&ssi0 {
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpb>;
>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart1: uart1 {
>> function = "uart1";
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index dfb5a7e1bb21..8837147e5a84 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -61,13 +61,30 @@
>> };
>>
>> cgu: jz4780-cgu@10000000 {
>> - compatible = "ingenic,jz4780-cgu";
>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>> +
>> + #clock-cells = <1>;
>>
>> clocks = <&ext>, <&rtc>;
>> clock-names = "ext", "rtc";
>>
>> - #clock-cells = <1>;
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,jz4780-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>> +
>> + #phy-cells = <0>;
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,jz4780-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> };
>>
>> tcu: timer@10002000 {
>> @@ -494,4 +511,24 @@
>>
>> status = "disabled";
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu JZ4780_CLK_UHC>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> index 1f1f896dd1f7..854fac58f45e 100644
>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -52,13 +52,43 @@
>> };
>>
>> cgu: x1000-cgu@10000000 {
>> - compatible = "ingenic,x1000-cgu";
>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1000-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,x1000-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1000_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <3>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -323,4 +353,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1000_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
>> b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> index b05dac3ae308..4831350efdf2 100644
>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> @@ -52,13 +52,38 @@
>> };
>>
>> cgu: x1830-cgu@10000000 {
>> - compatible = "ingenic,x1830-cgu";
>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1830-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1830_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <4>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -236,6 +261,13 @@
>> status = "disabled";
>> };
>>
>> + dtrng: trng@10072000 {
>> + compatible = "ingenic,x1830-dtrng";
>> + reg = <0x10072000 0xc>;
>> +
>> + clocks = <&cgu X1830_CLK_DTRNG>;
>> + };
>> +
>> pdma: dma-controller@13420000 {
>> compatible = "ingenic,x1830-dma";
>> reg = <0x13420000 0x400
>> @@ -311,4 +343,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1830_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> --
>> 2.11.0
>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-07 11:52 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards 周琰杰 (Zhou Yanjie)
2020-11-07 19:03 ` H. Nikolaus Schaller
2020-11-09 23:30 ` [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards Paul Cercueil
@ 2020-11-09 23:37 ` Paul Cercueil
2020-11-10 6:31 ` Zhou Yanjie
2 siblings, 1 reply; 16+ messages in thread
From: Paul Cercueil @ 2020-11-09 23:37 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, hns, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1000-Neo.
> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
> nodes for CU1830-Neo.
>
> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60
> +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60
> +++++++++++++++++++++++++++----
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
> arch/mips/boot/dts/ingenic/x1000.dtsi | 52
> ++++++++++++++++++++++++++-
> arch/mips/boot/dts/ingenic/x1830.dtsi | 54
> +++++++++++++++++++++++++++-
> 6 files changed, 267 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 75f5bfbf2c37..b31054a41754 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -93,6 +93,15 @@
> clock-frequency = <48000000>;
> };
>
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
> +};
> +
> &mmc0 {
> status = "okay";
>
> @@ -396,6 +405,13 @@
> status = "okay";
> };
>
> +&otg {
> + status = "okay";
> +
> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
> + assigned-clock-rates = <48000000>;
> +};
> +
> &pinctrl {
> pins_uart0: uart0 {
> function = "uart0";
> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> index 22a1066d637b..44d47d12db12 100644
> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1000.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1000_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
> OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the
> clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart2 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart2>;
> };
>
> +&ssi {
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpc>;
> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart2: uart2 {
> function = "uart2";
> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> index 640f96c00d63..7a56e344e429 100644
> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
> @@ -3,7 +3,7 @@
>
> #include "x1830.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/clock/ingenic,tcu.h>
> +#include <dt-bindings/clock/ingenic,sysost.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> @@ -31,6 +31,18 @@
> };
> };
>
> + ssi0: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-chipselects = <1>;
> +
> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
> + };
> +
> wlan_pwrseq: msc1-pwrseq {
> compatible = "mmc-pwrseq-simple";
>
> @@ -43,13 +55,19 @@
> clock-frequency = <24000000>;
> };
>
> -&tcu {
> +&cgu {
> + /*
> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
> higher
> + * precision.
> + */
> + assigned-clocks = <&cgu X1830_CLK_RTC>;
> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
> +};
> +
> +&ost {
> /* 1500 kHz for the system timer and clocksource */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
> OST_CLK_GLOBAL_TIMER>;
> assigned-clock-rates = <1500000>, <1500000>;
> -
> - /* Use channel #0 for the system timer channel #2 for the
> clocksource */
> - ingenic,pwm-channels-mask = <0xfa>;
> };
>
> &uart1 {
> @@ -59,6 +77,32 @@
> pinctrl-0 = <&pins_uart1>;
> };
>
> +&ssi0 {
> + status = "okay";
> +
> + spi-max-frequency = <50000000>;
> +
> + sc16is752: expander@0 {
> + compatible = "nxp,sc16is752";
> + reg = <0>; /* CE0 */
> + spi-max-frequency = <4000000>;
> +
> + clocks = <&exclk_sc16is752>;
> +
> + interrupt-parent = <&gpb>;
> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + exclk_sc16is752: sc16is752 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -135,6 +179,10 @@
> };
> };
>
> +&otg {
> + status = "okay";
> +};
> +
> &pinctrl {
> pins_uart1: uart1 {
> function = "uart1";
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index dfb5a7e1bb21..8837147e5a84 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -61,13 +61,30 @@
> };
>
> cgu: jz4780-cgu@10000000 {
> - compatible = "ingenic,jz4780-cgu";
> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
> +
> + #clock-cells = <1>;
>
> clocks = <&ext>, <&rtc>;
> clock-names = "ext", "rtc";
>
> - #clock-cells = <1>;
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,jz4780-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu JZ4780_CLK_OTG1>;
> +
> + #phy-cells = <0>;
Something I missed in my first email: you lack the "vcc-supply"
required property here. But I'm not sure what it should be linked to.
-Paul
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,jz4780-rng";
> + reg = <0xd8 0x8>;
> + };
> };
>
> tcu: timer@10002000 {
> @@ -494,4 +511,24 @@
>
> status = "disabled";
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu JZ4780_CLK_UHC>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index 1f1f896dd1f7..854fac58f45e 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -52,13 +52,43 @@
> };
>
> cgu: x1000-cgu@10000000 {
> - compatible = "ingenic,x1000-cgu";
> + compatible = "ingenic,x1000-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1000-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1000_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> +
> + rng: rng@d8 {
> + compatible = "ingenic,x1000-rng";
> + reg = <0xd8 0x8>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1000_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <3>;
> };
>
> tcu: timer@10002000 {
> @@ -323,4 +353,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1000-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1000_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index b05dac3ae308..4831350efdf2 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -52,13 +52,38 @@
> };
>
> cgu: x1830-cgu@10000000 {
> - compatible = "ingenic,x1830-cgu";
> + compatible = "ingenic,x1830-cgu", "simple-mfd";
> reg = <0x10000000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10000000 0x100>;
>
> #clock-cells = <1>;
>
> clocks = <&exclk>, <&rtclk>;
> clock-names = "ext", "rtc";
> +
> + otg_phy: usb-phy@3c {
> + compatible = "ingenic,x1830-phy";
> + reg = <0x3c 0x10>;
> +
> + clocks = <&cgu X1830_CLK_OTGPHY>;
> +
> + #phy-cells = <0>;
> + };
> + };
> +
> + ost: timer@12000000 {
> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
> + reg = <0x12000000 0x3c>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1830_CLK_OST>;
> + clock-names = "ost";
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <4>;
> };
>
> tcu: timer@10002000 {
> @@ -236,6 +261,13 @@
> status = "disabled";
> };
>
> + dtrng: trng@10072000 {
> + compatible = "ingenic,x1830-dtrng";
> + reg = <0x10072000 0xc>;
> +
> + clocks = <&cgu X1830_CLK_DTRNG>;
> + };
> +
> pdma: dma-controller@13420000 {
> compatible = "ingenic,x1830-dma";
> reg = <0x13420000 0x400
> @@ -311,4 +343,24 @@
> status = "disabled";
> };
> };
> +
> + otg: usb@13500000 {
> + compatible = "ingenic,x1830-otg", "snps,dwc2";
> + reg = <0x13500000 0x40000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <21>;
> +
> + clocks = <&cgu X1830_CLK_OTG>;
> + clock-names = "otg";
> +
> + phys = <&otg_phy>;
> + phy-names = "usb2-phy";
> +
> + g-rx-fifo-size = <768>;
> + g-np-tx-fifo-size = <256>;
> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
> +
> + status = "disabled";
> + };
> };
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-09 23:37 ` Paul Cercueil
@ 2020-11-10 6:31 ` Zhou Yanjie
2020-11-13 12:12 ` Paul Cercueil
0 siblings, 1 reply; 16+ messages in thread
From: Zhou Yanjie @ 2020-11-10 6:31 UTC (permalink / raw)
To: Paul Cercueil
Cc: tsbogend, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, hns, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Hi Paul,
On 2020/11/10 上午7:37, Paul Cercueil wrote:
>
>
> Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1000-Neo.
>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
>> nodes for CU1830-Neo.
>>
>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> ---
>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60
>> +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60
>> +++++++++++++++++++++++++++----
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41 +++++++++++++++++++--
>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52
>> ++++++++++++++++++++++++++-
>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54
>> +++++++++++++++++++++++++++-
>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
>> b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 75f5bfbf2c37..b31054a41754 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -93,6 +93,15 @@
>> clock-frequency = <48000000>;
>> };
>>
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>> +};
>> +
>> &mmc0 {
>> status = "okay";
>>
>> @@ -396,6 +405,13 @@
>> status = "okay";
>> };
>>
>> +&otg {
>> + status = "okay";
>> +
>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>> + assigned-clock-rates = <48000000>;
>> +};
>> +
>> &pinctrl {
>> pins_uart0: uart0 {
>> function = "uart0";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> index 22a1066d637b..44d47d12db12 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1000.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>> OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the
>> clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart2 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart2>;
>> };
>>
>> +&ssi {
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpc>;
>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart2: uart2 {
>> function = "uart2";
>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> index 640f96c00d63..7a56e344e429 100644
>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>> @@ -3,7 +3,7 @@
>>
>> #include "x1830.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/clock/ingenic,tcu.h>
>> +#include <dt-bindings/clock/ingenic,sysost.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> / {
>> @@ -31,6 +31,18 @@
>> };
>> };
>>
>> + ssi0: spi-gpio {
>> + compatible = "spi-gpio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-chipselects = <1>;
>> +
>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> wlan_pwrseq: msc1-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>>
>> @@ -43,13 +55,19 @@
>> clock-frequency = <24000000>;
>> };
>>
>> -&tcu {
>> +&cgu {
>> + /*
>> + * Use the 32.768 kHz oscillator as the parent of the RTC for a
>> higher
>> + * precision.
>> + */
>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>> +};
>> +
>> +&ost {
>> /* 1500 kHz for the system timer and clocksource */
>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>> OST_CLK_GLOBAL_TIMER>;
>> assigned-clock-rates = <1500000>, <1500000>;
>> -
>> - /* Use channel #0 for the system timer channel #2 for the
>> clocksource */
>> - ingenic,pwm-channels-mask = <0xfa>;
>> };
>>
>> &uart1 {
>> @@ -59,6 +77,32 @@
>> pinctrl-0 = <&pins_uart1>;
>> };
>>
>> +&ssi0 {
>> + status = "okay";
>> +
>> + spi-max-frequency = <50000000>;
>> +
>> + sc16is752: expander@0 {
>> + compatible = "nxp,sc16is752";
>> + reg = <0>; /* CE0 */
>> + spi-max-frequency = <4000000>;
>> +
>> + clocks = <&exclk_sc16is752>;
>> +
>> + interrupt-parent = <&gpb>;
>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + exclk_sc16is752: sc16is752 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <48000000>;
>> + };
>> + };
>> +};
>> +
>> &i2c0 {
>> status = "okay";
>>
>> @@ -135,6 +179,10 @@
>> };
>> };
>>
>> +&otg {
>> + status = "okay";
>> +};
>> +
>> &pinctrl {
>> pins_uart1: uart1 {
>> function = "uart1";
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index dfb5a7e1bb21..8837147e5a84 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -61,13 +61,30 @@
>> };
>>
>> cgu: jz4780-cgu@10000000 {
>> - compatible = "ingenic,jz4780-cgu";
>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>> +
>> + #clock-cells = <1>;
>>
>> clocks = <&ext>, <&rtc>;
>> clock-names = "ext", "rtc";
>>
>> - #clock-cells = <1>;
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,jz4780-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>> +
>> + #phy-cells = <0>;
>
> Something I missed in my first email: you lack the "vcc-supply"
> required property here. But I'm not sure what it should be linked to.
>
I checked the datasheet of JZ4780. There are 3 power pins rekated to
USB: VBUS, AVDUSB33, and AVDUSB25, but it is not clearly described on
the datasheet whether it is for the USB PHY or the USB controller. And
it is strange that now it can works properly without vcc-supply. Maybe
vcc-supply is not necessarily required? If so, should we mark it as
optional? On the other hand, if vcc-supply is indeed required, do we
need to add two new vccs to ensure one-to-on correspondence with the
aforementioned three power supplies?
Thanks and best regards!
> -Paul
>
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,jz4780-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> };
>>
>> tcu: timer@10002000 {
>> @@ -494,4 +511,24 @@
>>
>> status = "disabled";
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu JZ4780_CLK_UHC>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> index 1f1f896dd1f7..854fac58f45e 100644
>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -52,13 +52,43 @@
>> };
>>
>> cgu: x1000-cgu@10000000 {
>> - compatible = "ingenic,x1000-cgu";
>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1000-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> +
>> + rng: rng@d8 {
>> + compatible = "ingenic,x1000-rng";
>> + reg = <0xd8 0x8>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1000_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <3>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -323,4 +353,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1000_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
>> b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> index b05dac3ae308..4831350efdf2 100644
>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>> @@ -52,13 +52,38 @@
>> };
>>
>> cgu: x1830-cgu@10000000 {
>> - compatible = "ingenic,x1830-cgu";
>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>> reg = <0x10000000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10000000 0x100>;
>>
>> #clock-cells = <1>;
>>
>> clocks = <&exclk>, <&rtclk>;
>> clock-names = "ext", "rtc";
>> +
>> + otg_phy: usb-phy@3c {
>> + compatible = "ingenic,x1830-phy";
>> + reg = <0x3c 0x10>;
>> +
>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>> +
>> + #phy-cells = <0>;
>> + };
>> + };
>> +
>> + ost: timer@12000000 {
>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>> + reg = <0x12000000 0x3c>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1830_CLK_OST>;
>> + clock-names = "ost";
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <4>;
>> };
>>
>> tcu: timer@10002000 {
>> @@ -236,6 +261,13 @@
>> status = "disabled";
>> };
>>
>> + dtrng: trng@10072000 {
>> + compatible = "ingenic,x1830-dtrng";
>> + reg = <0x10072000 0xc>;
>> +
>> + clocks = <&cgu X1830_CLK_DTRNG>;
>> + };
>> +
>> pdma: dma-controller@13420000 {
>> compatible = "ingenic,x1830-dma";
>> reg = <0x13420000 0x400
>> @@ -311,4 +343,24 @@
>> status = "disabled";
>> };
>> };
>> +
>> + otg: usb@13500000 {
>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>> + reg = <0x13500000 0x40000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <21>;
>> +
>> + clocks = <&cgu X1830_CLK_OTG>;
>> + clock-names = "otg";
>> +
>> + phys = <&otg_phy>;
>> + phy-names = "usb2-phy";
>> +
>> + g-rx-fifo-size = <768>;
>> + g-np-tx-fifo-size = <256>;
>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>> +
>> + status = "disabled";
>> + };
>> };
>> --
>> 2.11.0
>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
2020-11-10 6:31 ` Zhou Yanjie
@ 2020-11-13 12:12 ` Paul Cercueil
0 siblings, 0 replies; 16+ messages in thread
From: Paul Cercueil @ 2020-11-13 12:12 UTC (permalink / raw)
To: Zhou Yanjie
Cc: tsbogend, robh+dt, linux-kernel, linux-mips, devicetree,
nixiaoming, paulburton, krzk, hns, ak, ebiederm, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Hi Zhou,
Le mar. 10 nov. 2020 à 14:31, Zhou Yanjie <zhouyanjie@wanyeetech.com>
a écrit :
> Hi Paul,
>
> On 2020/11/10 上午7:37, Paul Cercueil wrote:
>>
>>
>> Le sam. 7 nov. 2020 à 19:52, 周琰杰 (Zhou Yanjie)
>> \x7f<zhouyanjie@wanyeetech.com> a écrit :
>>> 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
>>> 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
>>> nodes for CU1000-Neo.
>>> 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830,
>>> SSI/CGU/OST/OTG/SC16IS752
>>> nodes for CU1830-Neo.
>>>
>>> Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>>> ---
>>> arch/mips/boot/dts/ingenic/ci20.dts | 16 +++++++++
>>> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 60
>>> \x7f\x7f+++++++++++++++++++++++++++----
>>> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 60
>>> \x7f\x7f+++++++++++++++++++++++++++----
>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 41
>>> +++++++++++++++++++--
>>> arch/mips/boot/dts/ingenic/x1000.dtsi | 52
>>> \x7f\x7f++++++++++++++++++++++++++-
>>> arch/mips/boot/dts/ingenic/x1830.dtsi | 54
>>> \x7f\x7f+++++++++++++++++++++++++++-
>>> 6 files changed, 267 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/ci20.dts
>>> index 75f5bfbf2c37..b31054a41754 100644
>>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>>> @@ -93,6 +93,15 @@
>>> clock-frequency = <48000000>;
>>> };
>>>
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for
>>> a \x7f\x7fhigher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu JZ4780_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu JZ4780_CLK_RTCLK>;
>>> +};
>>> +
>>> &mmc0 {
>>> status = "okay";
>>>
>>> @@ -396,6 +405,13 @@
>>> status = "okay";
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +
>>> + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>;
>>> + assigned-clock-rates = <48000000>;
>>> +};
>>> +
>>> &pinctrl {
>>> pins_uart0: uart0 {
>>> function = "uart0";
>>> diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> index 22a1066d637b..44d47d12db12 100644
>>> --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
>>> @@ -3,7 +3,7 @@
>>>
>>> #include "x1000.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>
>>> / {
>>> @@ -31,6 +31,18 @@
>>> };
>>> };
>>>
>>> + ssi: spi-gpio {
>>> + compatible = "spi-gpio";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + num-chipselects = <1>;
>>> +
>>> + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
>>> + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
>>> + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
>>> + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
>>> + };
>>> +
>>> wlan_pwrseq: msc1-pwrseq {
>>> compatible = "mmc-pwrseq-simple";
>>>
>>> @@ -43,13 +55,19 @@
>>> clock-frequency = <24000000>;
>>> };
>>>
>>> -&tcu {
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for
>>> a \x7f\x7fhigher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu X1000_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
>>> +};
>>> +
>>> +&ost {
>>> /* 1500 kHz for the system timer and clocksource */
>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>>> \x7f\x7fOST_CLK_GLOBAL_TIMER>;
>>> assigned-clock-rates = <1500000>, <1500000>;
>>> -
>>> - /* Use channel #0 for the system timer channel #2 for the
>>> \x7f\x7fclocksource */
>>> - ingenic,pwm-channels-mask = <0xfa>;
>>> };
>>>
>>> &uart2 {
>>> @@ -59,6 +77,32 @@
>>> pinctrl-0 = <&pins_uart2>;
>>> };
>>>
>>> +&ssi {
>>> + status = "okay";
>>> +
>>> + spi-max-frequency = <50000000>;
>>> +
>>> + sc16is752: expander@0 {
>>> + compatible = "nxp,sc16is752";
>>> + reg = <0>; /* CE0 */
>>> + spi-max-frequency = <4000000>;
>>> +
>>> + clocks = <&exclk_sc16is752>;
>>> +
>>> + interrupt-parent = <&gpc>;
>>> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
>>> +
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> +
>>> + exclk_sc16is752: sc16is752 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <48000000>;
>>> + };
>>> + };
>>> +};
>>> +
>>> &i2c0 {
>>> status = "okay";
>>>
>>> @@ -135,6 +179,10 @@
>>> };
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +};
>>> +
>>> &pinctrl {
>>> pins_uart2: uart2 {
>>> function = "uart2";
>>> diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> index 640f96c00d63..7a56e344e429 100644
>>> --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
>>> @@ -3,7 +3,7 @@
>>>
>>> #include "x1830.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>> -#include <dt-bindings/clock/ingenic,tcu.h>
>>> +#include <dt-bindings/clock/ingenic,sysost.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>
>>> / {
>>> @@ -31,6 +31,18 @@
>>> };
>>> };
>>>
>>> + ssi0: spi-gpio {
>>> + compatible = "spi-gpio";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + num-chipselects = <1>;
>>> +
>>> + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
>>> + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
>>> + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
>>> + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
>>> + };
>>> +
>>> wlan_pwrseq: msc1-pwrseq {
>>> compatible = "mmc-pwrseq-simple";
>>>
>>> @@ -43,13 +55,19 @@
>>> clock-frequency = <24000000>;
>>> };
>>>
>>> -&tcu {
>>> +&cgu {
>>> + /*
>>> + * Use the 32.768 kHz oscillator as the parent of the RTC for
>>> a \x7f\x7fhigher
>>> + * precision.
>>> + */
>>> + assigned-clocks = <&cgu X1830_CLK_RTC>;
>>> + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
>>> +};
>>> +
>>> +&ost {
>>> /* 1500 kHz for the system timer and clocksource */
>>> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
>>> + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost
>>> \x7f\x7fOST_CLK_GLOBAL_TIMER>;
>>> assigned-clock-rates = <1500000>, <1500000>;
>>> -
>>> - /* Use channel #0 for the system timer channel #2 for the
>>> \x7f\x7fclocksource */
>>> - ingenic,pwm-channels-mask = <0xfa>;
>>> };
>>>
>>> &uart1 {
>>> @@ -59,6 +77,32 @@
>>> pinctrl-0 = <&pins_uart1>;
>>> };
>>>
>>> +&ssi0 {
>>> + status = "okay";
>>> +
>>> + spi-max-frequency = <50000000>;
>>> +
>>> + sc16is752: expander@0 {
>>> + compatible = "nxp,sc16is752";
>>> + reg = <0>; /* CE0 */
>>> + spi-max-frequency = <4000000>;
>>> +
>>> + clocks = <&exclk_sc16is752>;
>>> +
>>> + interrupt-parent = <&gpb>;
>>> + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>> +
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> +
>>> + exclk_sc16is752: sc16is752 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <48000000>;
>>> + };
>>> + };
>>> +};
>>> +
>>> &i2c0 {
>>> status = "okay";
>>>
>>> @@ -135,6 +179,10 @@
>>> };
>>> };
>>>
>>> +&otg {
>>> + status = "okay";
>>> +};
>>> +
>>> &pinctrl {
>>> pins_uart1: uart1 {
>>> function = "uart1";
>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> index dfb5a7e1bb21..8837147e5a84 100644
>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> @@ -61,13 +61,30 @@
>>> };
>>>
>>> cgu: jz4780-cgu@10000000 {
>>> - compatible = "ingenic,jz4780-cgu";
>>> + compatible = "ingenic,jz4780-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>> +
>>> + #clock-cells = <1>;
>>>
>>> clocks = <&ext>, <&rtc>;
>>> clock-names = "ext", "rtc";
>>>
>>> - #clock-cells = <1>;
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,jz4780-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu JZ4780_CLK_OTG1>;
>>> +
>>> + #phy-cells = <0>;
>>
>> Something I missed in my first email: you lack the "vcc-supply"
>> \x7frequired property here. But I'm not sure what it should be linked
>> to.
>>
>
> I checked the datasheet of JZ4780. There are 3 power pins rekated to
> USB: VBUS, AVDUSB33, and AVDUSB25, but it is not clearly described on
> the datasheet whether it is for the USB PHY or the USB controller.
> And it is strange that now it can works properly without vcc-supply.
> Maybe vcc-supply is not necessarily required? If so, should we mark
> it as optional? On the other hand, if vcc-supply is indeed required,
> do we need to add two new vccs to ensure one-to-on correspondence
> with the aforementioned three power supplies?
On the GCW-Zero, USB (gadget) doesn't work unless a power supply is
enabled in the external ACT8600 chip. We don't have the design files so
we don't really know where is that power supply actually connected to,
so we assumed it was the USB PHY. I don't really know what's the play
here - maybe you don't need a vcc-supply (and in this case it should be
made optional in the binding), maybe you do need one but it's enabled
by default (maybe disabled through a GPIO?).
The easiest fix would be to set:
&otg_phy {
vcc-supply = <&vcc>;
}
in the ci20.dts.
But as I said above - I'm not really sure what to do here.
Cheers,
-Paul
>>> + };
>>> +
>>> + rng: rng@d8 {
>>> + compatible = "ingenic,jz4780-rng";
>>> + reg = <0xd8 0x8>;
>>> + };
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -494,4 +511,24 @@
>>>
>>> status = "disabled";
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,jz4780-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu JZ4780_CLK_UHC>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> index 1f1f896dd1f7..854fac58f45e 100644
>>> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>>> @@ -52,13 +52,43 @@
>>> };
>>>
>>> cgu: x1000-cgu@10000000 {
>>> - compatible = "ingenic,x1000-cgu";
>>> + compatible = "ingenic,x1000-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>>
>>> #clock-cells = <1>;
>>>
>>> clocks = <&exclk>, <&rtclk>;
>>> clock-names = "ext", "rtc";
>>> +
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,x1000-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OTGPHY>;
>>> +
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + rng: rng@d8 {
>>> + compatible = "ingenic,x1000-rng";
>>> + reg = <0xd8 0x8>;
>>> + };
>>> + };
>>> +
>>> + ost: timer@12000000 {
>>> + compatible = "ingenic,x1000-ost";
>>> + reg = <0x12000000 0x3c>;
>>> +
>>> + #clock-cells = <1>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OST>;
>>> + clock-names = "ost";
>>> +
>>> + interrupt-parent = <&cpuintc>;
>>> + interrupts = <3>;
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -323,4 +353,24 @@
>>> status = "disabled";
>>> };
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,x1000-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu X1000_CLK_OTG>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> \x7f\x7fb/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> index b05dac3ae308..4831350efdf2 100644
>>> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
>>> @@ -52,13 +52,38 @@
>>> };
>>>
>>> cgu: x1830-cgu@10000000 {
>>> - compatible = "ingenic,x1830-cgu";
>>> + compatible = "ingenic,x1830-cgu", "simple-mfd";
>>> reg = <0x10000000 0x100>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x10000000 0x100>;
>>>
>>> #clock-cells = <1>;
>>>
>>> clocks = <&exclk>, <&rtclk>;
>>> clock-names = "ext", "rtc";
>>> +
>>> + otg_phy: usb-phy@3c {
>>> + compatible = "ingenic,x1830-phy";
>>> + reg = <0x3c 0x10>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OTGPHY>;
>>> +
>>> + #phy-cells = <0>;
>>> + };
>>> + };
>>> +
>>> + ost: timer@12000000 {
>>> + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
>>> + reg = <0x12000000 0x3c>;
>>> +
>>> + #clock-cells = <1>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OST>;
>>> + clock-names = "ost";
>>> +
>>> + interrupt-parent = <&cpuintc>;
>>> + interrupts = <4>;
>>> };
>>>
>>> tcu: timer@10002000 {
>>> @@ -236,6 +261,13 @@
>>> status = "disabled";
>>> };
>>>
>>> + dtrng: trng@10072000 {
>>> + compatible = "ingenic,x1830-dtrng";
>>> + reg = <0x10072000 0xc>;
>>> +
>>> + clocks = <&cgu X1830_CLK_DTRNG>;
>>> + };
>>> +
>>> pdma: dma-controller@13420000 {
>>> compatible = "ingenic,x1830-dma";
>>> reg = <0x13420000 0x400
>>> @@ -311,4 +343,24 @@
>>> status = "disabled";
>>> };
>>> };
>>> +
>>> + otg: usb@13500000 {
>>> + compatible = "ingenic,x1830-otg", "snps,dwc2";
>>> + reg = <0x13500000 0x40000>;
>>> +
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <21>;
>>> +
>>> + clocks = <&cgu X1830_CLK_OTG>;
>>> + clock-names = "otg";
>>> +
>>> + phys = <&otg_phy>;
>>> + phy-names = "usb2-phy";
>>> +
>>> + g-rx-fifo-size = <768>;
>>> + g-np-tx-fifo-size = <256>;
>>> + g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
>>> +
>>> + status = "disabled";
>>> + };
>>> };
>>> --
>>> 2.11.0
>>>
>>
^ permalink raw reply [flat|nested] 16+ messages in thread