* [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs @ 2020-11-16 16:24 Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT ` (4 more replies) 0 siblings, 5 replies; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT Hello, Ocelot SoC belongs to a larger family of SoCs which use the same interrupt controller with a few variation. This series of patches add support for Luton, Serval and Jaguar2, they are all MIPS based. The first patches of the series also updates the binding documentation with the new compatible strings. Gregory Changelog: v2 -> v3 - Fix new-line-at-end-of-file error in the yaml file v1 -> v2: - Convert the binding to yaml - Squashed the patches adding new binding in a single one Gregory CLEMENT (5): dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers irqchip: ocelot: Add support for Luton platforms irqchip: ocelot: Add support for Serval platforms irqchip: ocelot: Add support for Jaguar2 platforms .../mscc,ocelot-icpu-intr.txt | 21 -- .../mscc,ocelot-icpu-intr.yaml | 63 ++++++ drivers/irqchip/irq-mscc-ocelot.c | 183 ++++++++++++++++-- 3 files changed, 225 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml -- 2.29.2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT @ 2020-11-16 16:24 ` Gregory CLEMENT 2020-11-18 20:50 ` Rob Herring 2020-11-16 16:24 ` [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT ` (3 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt Controller to YAML format Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- .../mscc,ocelot-icpu-intr.txt | 21 ------- .../mscc,ocelot-icpu-intr.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt deleted file mode 100644 index f5baeccb689f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Microsemi Ocelot SoC ICPU Interrupt Controller - -Required properties: - -- compatible : should be "mscc,ocelot-icpu-intr" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - - intc: interrupt-controller@70000070 { - compatible = "mscc,ocelot-icpu-intr"; - reg = <0x70000070 0x70>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml new file mode 100644 index 000000000000..3a537635a859 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microsemi Ocelot SoC ICPU Interrupt Controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + the Microsemi Ocelot interrupt controller that is part of the + ICPU. It is connected directly to the MIPS core interrupt + controller. + +properties: + compatible: + items: + - enum: + - mscc,ocelot-icpu-intr + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + +additionalProperties: false + +examples: + - | + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; +... -- 2.29.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema 2020-11-16 16:24 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT @ 2020-11-18 20:50 ` Rob Herring 0 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2020-11-18 20:50 UTC (permalink / raw) To: Gregory CLEMENT Cc: devicetree, Thomas Gleixner, Lars Povlsen, Marc Zyngier, Steen.Hegelund, Alexandre Belloni, Rob Herring, Thomas Petazzoni, linux-kernel, Jason Cooper On Mon, 16 Nov 2020 17:24:23 +0100, Gregory CLEMENT wrote: > Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt > Controller to YAML format > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > .../mscc,ocelot-icpu-intr.txt | 21 ------- > .../mscc,ocelot-icpu-intr.yaml | 59 +++++++++++++++++++ > 2 files changed, 59 insertions(+), 21 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.example.dt.yaml: interrupt-controller@70000070: '#address-cells' is a required property From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml See https://patchwork.ozlabs.org/patch/1401029 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT @ 2020-11-16 16:24 ` Gregory CLEMENT 2020-11-18 10:35 ` Alexandre Belloni 2020-11-16 16:24 ` [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT ` (2 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT Add the Device Tree binding documentation for the Microsemi Jaguar2, Luton and Serval interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index 3a537635a859..5483ed7062ba 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -21,7 +21,11 @@ properties: compatible: items: - enum: + - mscc,jaguar2-icpu-intr + - mscc,luton-icpu-intr - mscc,ocelot-icpu-intr + - mscc,serval-icpu-intr + '#interrupt-cells': const: 1 -- 2.29.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers 2020-11-16 16:24 ` [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT @ 2020-11-18 10:35 ` Alexandre Belloni 0 siblings, 0 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-11-18 10:35 UTC (permalink / raw) To: Gregory CLEMENT Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen, Steen.Hegelund Hello, On 16/11/2020 17:24:24+0100, Gregory CLEMENT wrote: > Add the Device Tree binding documentation for the Microsemi Jaguar2, > Luton and Serval interrupt controller that is part of the ICPU. It is > connected directly to the MIPS core interrupt controller. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > index 3a537635a859..5483ed7062ba 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > @@ -21,7 +21,11 @@ properties: > compatible: > items: > - enum: > + - mscc,jaguar2-icpu-intr > + - mscc,luton-icpu-intr > - mscc,ocelot-icpu-intr > + - mscc,serval-icpu-intr > + Spurious blank line > > '#interrupt-cells': > const: 1 > -- > 2.29.2 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT @ 2020-11-16 16:24 ` Gregory CLEMENT 2020-11-18 10:45 ` Alexandre Belloni 2020-11-18 12:38 ` Marc Zyngier 2020-11-16 16:24 ` [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT 4 siblings, 2 replies; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT This patch extends irqchip driver for oceleot to be used with an other vcoreiii base platform: Luton. Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- drivers/irqchip/irq-mscc-ocelot.c | 145 +++++++++++++++++++++++++----- 1 file changed, 123 insertions(+), 22 deletions(-) diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index 88143c0b700c..9964800c53c2 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -12,39 +12,115 @@ #include <linux/irqchip/chained_irq.h> #include <linux/interrupt.h> -#define ICPU_CFG_INTR_INTR_STICKY 0x10 -#define ICPU_CFG_INTR_INTR_ENA 0x18 -#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c -#define ICPU_CFG_INTR_INTR_ENA_SET 0x20 -#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x)) -#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x)) - -#define OCELOT_NR_IRQ 24 +#define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) (_p->reg_off_ident + 0x4 * (x)) +#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) (_p->reg_off_trigger + 0x4 * (x)) + +#define FLAGS_NEED_INIT_ENABLE BIT(0) +#define FLAGS_FORCE_LUTON_STYLE BIT(1) +#define FLAGS_HAS_TRIGGER BIT(2) + +struct chip_props { + u32 flags; + u32 reg_off_sticky; + u32 reg_off_ena; + u32 reg_off_ena_clr; + u32 reg_off_ena_set; + u32 reg_off_ident; + u32 reg_off_trigger; + u32 reg_off_force; + u32 reg_off_ena_irq0; + u32 n_irq; +}; + +static const struct chip_props ocelot_props = { + .flags = FLAGS_HAS_TRIGGER, + .reg_off_sticky = 0x10, + .reg_off_ena = 0x18, + .reg_off_ena_clr = 0x1c, + .reg_off_ena_set = 0x20, + .reg_off_ident = 0x38, + .reg_off_trigger = 0x5c, + .reg_off_force = 0xc, + .n_irq = 24, +}; + +static const struct chip_props luton_props = { + .flags = FLAGS_NEED_INIT_ENABLE | + FLAGS_FORCE_LUTON_STYLE, + .reg_off_sticky = 0, + .reg_off_ena = 0x4, + .reg_off_ena_clr = 0x8, + .reg_off_ena_set = 0xc, + .reg_off_ident = 0x18, + .reg_off_trigger = 0, + .reg_off_force = 0x38, + .reg_off_ena_irq0 = 0x14, + .n_irq = 28, +}; static void ocelot_irq_unmask(struct irq_data *data) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + struct irq_domain *d = data->domain; + struct chip_props *p = d->host_data; struct irq_chip_type *ct = irq_data_get_chip_type(data); unsigned int mask = data->mask; u32 val; irq_gc_lock(gc); - val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) | - irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1)); - if (!(val & mask)) - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY); + if (p->flags & FLAGS_HAS_TRIGGER) { + val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | + irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); + if (!(val & mask)) + irq_reg_writel(gc, mask, p->reg_off_sticky); + } *ct->mask_cache &= ~mask; - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET); + irq_reg_writel(gc, mask, p->reg_off_ena_set); irq_gc_unlock(gc); } +static void luton_irq_force(struct irq_data *data, + struct irq_chip_generic *gc, + struct chip_props *p) +{ + int off = p->reg_off_force + (data->hwirq * sizeof(u32)); + u32 val = irq_reg_readl(gc, off); + + irq_reg_writel(gc, val | BIT(3), off); +} + +static int ocelot_irq_force(struct irq_data *data, + enum irqchip_irq_state which, bool state) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + struct irq_domain *d = data->domain; + struct chip_props *p = d->host_data; + int ret = -EINVAL; + + /* Only supports triggering */ + if ((which == IRQCHIP_STATE_PENDING || + which == IRQCHIP_STATE_ACTIVE) && + state && p->reg_off_force) { + if (p->flags & FLAGS_FORCE_LUTON_STYLE) + /* Config register style */ + luton_irq_force(data, gc, p); + else + /* New, bitmask style */ + irq_reg_writel(gc, data->mask, p->reg_off_force); + ret = 0; + } + + return ret; +} + static void ocelot_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_domain *d = irq_desc_get_handler_data(desc); + struct chip_props *p = d->host_data; struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); - u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0)); + u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0)); chained_irq_enter(chip, desc); @@ -58,25 +134,28 @@ static void ocelot_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int __init ocelot_irq_init(struct device_node *node, - struct device_node *parent) +static int __init vcoreiii_irq_init(struct device_node *node, + struct device_node *parent, + const struct chip_props *p) { struct irq_domain *domain; struct irq_chip_generic *gc; int parent_irq, ret; + pr_info("%s: Load, %d irqs\n", node->name, p->n_irq); + parent_irq = irq_of_parse_and_map(node, 0); if (!parent_irq) return -EINVAL; - domain = irq_domain_add_linear(node, OCELOT_NR_IRQ, + domain = irq_domain_add_linear(node, p->n_irq, &irq_generic_chip_ops, NULL); if (!domain) { pr_err("%pOFn: unable to add irq domain\n", node); return -ENOMEM; } - ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1, + ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1, "icpu", handle_level_irq, 0, 0, 0); if (ret) { @@ -92,16 +171,23 @@ static int __init ocelot_irq_init(struct device_node *node, goto err_gc_free; } - gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY; - gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; + gc->chip_types[0].regs.ack = p->reg_off_sticky; + gc->chip_types[0].regs.mask = p->reg_off_ena_clr; gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; + gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; + gc->chip_types[0].chip.irq_set_irqchip_state = ocelot_irq_force; /* Mask and ack all interrupts */ - irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA); - irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY); + irq_reg_writel(gc, 0, p->reg_off_ena); + irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky); + + /* Overall init */ + if (p->flags & FLAGS_NEED_INIT_ENABLE) + irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0); + domain->host_data = (void *)p; irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler, domain); @@ -115,4 +201,19 @@ static int __init ocelot_irq_init(struct device_node *node, return ret; } + +static int __init ocelot_irq_init(struct device_node *node, + struct device_node *parent) +{ + return vcoreiii_irq_init(node, parent, &ocelot_props); +} + IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init); + +static int __init luton_irq_init(struct device_node *node, + struct device_node *parent) +{ + return vcoreiii_irq_init(node, parent, &luton_props); +} + +IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); -- 2.29.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms 2020-11-16 16:24 ` [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT @ 2020-11-18 10:45 ` Alexandre Belloni 2020-11-18 12:38 ` Marc Zyngier 1 sibling, 0 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-11-18 10:45 UTC (permalink / raw) To: Gregory CLEMENT Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen, Steen.Hegelund Hi, On 16/11/2020 17:24:25+0100, Gregory CLEMENT wrote: > static void ocelot_irq_unmask(struct irq_data *data) > { > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); > + struct irq_domain *d = data->domain; > + struct chip_props *p = d->host_data; > struct irq_chip_type *ct = irq_data_get_chip_type(data); > unsigned int mask = data->mask; > u32 val; > > irq_gc_lock(gc); > - val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) | > - irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1)); > - if (!(val & mask)) > - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY); > + if (p->flags & FLAGS_HAS_TRIGGER) { > + val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | > + irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); > + if (!(val & mask)) > + irq_reg_writel(gc, mask, p->reg_off_sticky); > + } > > *ct->mask_cache &= ~mask; > - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET); > + irq_reg_writel(gc, mask, p->reg_off_ena_set); > irq_gc_unlock(gc); > } Looking at that again, I think you should leave this function as is... > > +static void luton_irq_force(struct irq_data *data, > + struct irq_chip_generic *gc, > + struct chip_props *p) > +{ > + int off = p->reg_off_force + (data->hwirq * sizeof(u32)); > + u32 val = irq_reg_readl(gc, off); > + > + irq_reg_writel(gc, val | BIT(3), off); > +} > + > +static int ocelot_irq_force(struct irq_data *data, > + enum irqchip_irq_state which, bool state) > +{ > + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); > + struct irq_domain *d = data->domain; > + struct chip_props *p = d->host_data; > + int ret = -EINVAL; > + > + /* Only supports triggering */ > + if ((which == IRQCHIP_STATE_PENDING || > + which == IRQCHIP_STATE_ACTIVE) && > + state && p->reg_off_force) { > + if (p->flags & FLAGS_FORCE_LUTON_STYLE) > + /* Config register style */ > + luton_irq_force(data, gc, p); > + else > + /* New, bitmask style */ > + irq_reg_writel(gc, data->mask, p->reg_off_force); > + ret = 0; > + } > + > + return ret; > +} > + I think the addition of the force function may be separated in an different patch. > -static int __init ocelot_irq_init(struct device_node *node, > - struct device_node *parent) > +static int __init vcoreiii_irq_init(struct device_node *node, > + struct device_node *parent, > + const struct chip_props *p) > { > struct irq_domain *domain; > struct irq_chip_generic *gc; > int parent_irq, ret; > > + pr_info("%s: Load, %d irqs\n", node->name, p->n_irq); > + Is this necessary? > parent_irq = irq_of_parse_and_map(node, 0); > if (!parent_irq) > return -EINVAL; > > - domain = irq_domain_add_linear(node, OCELOT_NR_IRQ, > + domain = irq_domain_add_linear(node, p->n_irq, > &irq_generic_chip_ops, NULL); > if (!domain) { > pr_err("%pOFn: unable to add irq domain\n", node); > return -ENOMEM; > } > > - ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1, > + ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1, > "icpu", handle_level_irq, > 0, 0, 0); > if (ret) { > @@ -92,16 +171,23 @@ static int __init ocelot_irq_init(struct device_node *node, > goto err_gc_free; > } > > - gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY; > - gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; > + gc->chip_types[0].regs.ack = p->reg_off_sticky; > + gc->chip_types[0].regs.mask = p->reg_off_ena_clr; > gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; > gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; > gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; > + gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; This is assigned the same member twice. As said, you can probably leave ocelot_irq_unmask so we avoid having an if in the hot path. You should test here for triggers and if they are not available, then you can use regs.enable/regs.disable and irq_gc_mask_disable_reg and irq_gc_unmask_enable_reg instead of regs.mask and irq_gc_mask_set_bit/ocelot_irq_unmask -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms 2020-11-16 16:24 ` [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT 2020-11-18 10:45 ` Alexandre Belloni @ 2020-11-18 12:38 ` Marc Zyngier 1 sibling, 0 replies; 12+ messages in thread From: Marc Zyngier @ 2020-11-18 12:38 UTC (permalink / raw) To: Gregory CLEMENT Cc: Thomas Gleixner, Jason Cooper, linux-kernel, Rob Herring, devicetree, Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund On 2020-11-16 16:24, Gregory CLEMENT wrote: > This patch extends irqchip driver for oceleot to be used with an other > vcoreiii base platform: Luton. > > Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > drivers/irqchip/irq-mscc-ocelot.c | 145 +++++++++++++++++++++++++----- > 1 file changed, 123 insertions(+), 22 deletions(-) > > diff --git a/drivers/irqchip/irq-mscc-ocelot.c > b/drivers/irqchip/irq-mscc-ocelot.c > index 88143c0b700c..9964800c53c2 100644 > --- a/drivers/irqchip/irq-mscc-ocelot.c > +++ b/drivers/irqchip/irq-mscc-ocelot.c > @@ -12,39 +12,115 @@ > #include <linux/irqchip/chained_irq.h> > #include <linux/interrupt.h> > > -#define ICPU_CFG_INTR_INTR_STICKY 0x10 > -#define ICPU_CFG_INTR_INTR_ENA 0x18 > -#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c > -#define ICPU_CFG_INTR_INTR_ENA_SET 0x20 > -#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x)) > -#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x)) > - > -#define OCELOT_NR_IRQ 24 > +#define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) (_p->reg_off_ident + 0x4 * > (x)) > +#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) (_p->reg_off_trigger + 0x4 * > (x)) > + > +#define FLAGS_NEED_INIT_ENABLE BIT(0) > +#define FLAGS_FORCE_LUTON_STYLE BIT(1) > +#define FLAGS_HAS_TRIGGER BIT(2) > + > +struct chip_props { > + u32 flags; > + u32 reg_off_sticky; > + u32 reg_off_ena; > + u32 reg_off_ena_clr; > + u32 reg_off_ena_set; > + u32 reg_off_ident; > + u32 reg_off_trigger; > + u32 reg_off_force; > + u32 reg_off_ena_irq0; Do all these fields need to be u32s? > + u32 n_irq; > +}; > + > +static const struct chip_props ocelot_props = { > + .flags = FLAGS_HAS_TRIGGER, > + .reg_off_sticky = 0x10, > + .reg_off_ena = 0x18, > + .reg_off_ena_clr = 0x1c, > + .reg_off_ena_set = 0x20, > + .reg_off_ident = 0x38, > + .reg_off_trigger = 0x5c, > + .reg_off_force = 0xc, > + .n_irq = 24, > +}; > + > +static const struct chip_props luton_props = { > + .flags = FLAGS_NEED_INIT_ENABLE | > + FLAGS_FORCE_LUTON_STYLE, LUTON_STYLE doesn't quite convey the idea of what this implies. Please use a name that actually means something (other than the city north of London). And force what exactly? > + .reg_off_sticky = 0, > + .reg_off_ena = 0x4, > + .reg_off_ena_clr = 0x8, > + .reg_off_ena_set = 0xc, > + .reg_off_ident = 0x18, > + .reg_off_trigger = 0, If this field doesn't exist (because the matching flag isn't set), don't list it. > + .reg_off_force = 0x38, > + .reg_off_ena_irq0 = 0x14, > + .n_irq = 28, > +}; Please split this patch in two: rework the Ocelot driver to the "new" style in one patch, then introduce new platform in another. > > static void ocelot_irq_unmask(struct irq_data *data) > { > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); > + struct irq_domain *d = data->domain; > + struct chip_props *p = d->host_data; > struct irq_chip_type *ct = irq_data_get_chip_type(data); > unsigned int mask = data->mask; > u32 val; > > irq_gc_lock(gc); > - val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) | > - irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1)); > - if (!(val & mask)) > - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY); > + if (p->flags & FLAGS_HAS_TRIGGER) { > + val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | > + irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); > + if (!(val & mask)) > + irq_reg_writel(gc, mask, p->reg_off_sticky); > + } > > *ct->mask_cache &= ~mask; > - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET); > + irq_reg_writel(gc, mask, p->reg_off_ena_set); > irq_gc_unlock(gc); > } > > +static void luton_irq_force(struct irq_data *data, > + struct irq_chip_generic *gc, > + struct chip_props *p) > +{ > + int off = p->reg_off_force + (data->hwirq * sizeof(u32)); > + u32 val = irq_reg_readl(gc, off); > + > + irq_reg_writel(gc, val | BIT(3), off); > +} > + > +static int ocelot_irq_force(struct irq_data *data, > + enum irqchip_irq_state which, bool state) Please use a name that matches the same of the API. > +{ > + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); > + struct irq_domain *d = data->domain; > + struct chip_props *p = d->host_data; > + int ret = -EINVAL; > + > + /* Only supports triggering */ > + if ((which == IRQCHIP_STATE_PENDING || > + which == IRQCHIP_STATE_ACTIVE) && PENDING and ACTIVE are two very different things, and yet you handle them the same way. Which one does your interrupt controller support? > + state && p->reg_off_force) { > + if (p->flags & FLAGS_FORCE_LUTON_STYLE) > + /* Config register style */ > + luton_irq_force(data, gc, p); > + else > + /* New, bitmask style */ > + irq_reg_writel(gc, data->mask, p->reg_off_force); > + ret = 0; > + } > + > + return ret; > +} > + > static void ocelot_irq_handler(struct irq_desc *desc) > { > struct irq_chip *chip = irq_desc_get_chip(desc); > struct irq_domain *d = irq_desc_get_handler_data(desc); > + struct chip_props *p = d->host_data; > struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); > - u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0)); > + u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0)); > > chained_irq_enter(chip, desc); > > @@ -58,25 +134,28 @@ static void ocelot_irq_handler(struct irq_desc > *desc) > chained_irq_exit(chip, desc); > } > > -static int __init ocelot_irq_init(struct device_node *node, > - struct device_node *parent) > +static int __init vcoreiii_irq_init(struct device_node *node, > + struct device_node *parent, > + const struct chip_props *p) > { > struct irq_domain *domain; > struct irq_chip_generic *gc; > int parent_irq, ret; > > + pr_info("%s: Load, %d irqs\n", node->name, p->n_irq); If you must print something, use %pOFn, just like in the rest of the driver. > + > parent_irq = irq_of_parse_and_map(node, 0); > if (!parent_irq) > return -EINVAL; > > - domain = irq_domain_add_linear(node, OCELOT_NR_IRQ, > + domain = irq_domain_add_linear(node, p->n_irq, > &irq_generic_chip_ops, NULL); > if (!domain) { > pr_err("%pOFn: unable to add irq domain\n", node); > return -ENOMEM; > } > > - ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1, > + ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1, > "icpu", handle_level_irq, > 0, 0, 0); > if (ret) { > @@ -92,16 +171,23 @@ static int __init ocelot_irq_init(struct > device_node *node, > goto err_gc_free; > } > > - gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY; > - gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; > + gc->chip_types[0].regs.ack = p->reg_off_sticky; > + gc->chip_types[0].regs.mask = p->reg_off_ena_clr; > gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; > gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; > gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; > + gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; > + gc->chip_types[0].chip.irq_set_irqchip_state = ocelot_irq_force; > > /* Mask and ack all interrupts */ > - irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA); > - irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY); > + irq_reg_writel(gc, 0, p->reg_off_ena); > + irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky); > + > + /* Overall init */ > + if (p->flags & FLAGS_NEED_INIT_ENABLE) > + irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0); > > + domain->host_data = (void *)p; Useless cast. > irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler, > domain); > > @@ -115,4 +201,19 @@ static int __init ocelot_irq_init(struct > device_node *node, > > return ret; > } > + > +static int __init ocelot_irq_init(struct device_node *node, > + struct device_node *parent) > +{ > + return vcoreiii_irq_init(node, parent, &ocelot_props); > +} > + > IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", > ocelot_irq_init); > + > +static int __init luton_irq_init(struct device_node *node, > + struct device_node *parent) > +{ > + return vcoreiii_irq_init(node, parent, &luton_props); > +} > + > +IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT ` (2 preceding siblings ...) 2020-11-16 16:24 ` [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT @ 2020-11-16 16:24 ` Gregory CLEMENT 2020-11-18 10:46 ` Alexandre Belloni 2020-11-16 16:24 ` [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT 4 siblings, 1 reply; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT This patch extends irqchip driver for ocelot to be used with an other vcoreiii base platform: Serval. Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index 9964800c53c2..584af3b0a9e2 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -44,6 +44,18 @@ static const struct chip_props ocelot_props = { .n_irq = 24, }; +static const struct chip_props serval_props = { + .flags = FLAGS_HAS_TRIGGER, + .reg_off_sticky = 0xc, + .reg_off_ena = 0x14, + .reg_off_ena_clr = 0x18, + .reg_off_ena_set = 0x1c, + .reg_off_ident = 0x20, + .reg_off_trigger = 0x4, + .reg_off_force = 0x8, + .n_irq = 24, +}; + static const struct chip_props luton_props = { .flags = FLAGS_NEED_INIT_ENABLE | FLAGS_FORCE_LUTON_STYLE, @@ -210,6 +222,14 @@ static int __init ocelot_irq_init(struct device_node *node, IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init); +static int __init serval_irq_init(struct device_node *node, + struct device_node *parent) +{ + return vcoreiii_irq_init(node, parent, &serval_props); +} + +IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init); + static int __init luton_irq_init(struct device_node *node, struct device_node *parent) { -- 2.29.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms 2020-11-16 16:24 ` [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT @ 2020-11-18 10:46 ` Alexandre Belloni 0 siblings, 0 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-11-18 10:46 UTC (permalink / raw) To: Gregory CLEMENT Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen, Steen.Hegelund On 16/11/2020 17:24:26+0100, Gregory CLEMENT wrote: > This patch extends irqchip driver for ocelot to be used with an other > vcoreiii base platform: Serval. > > Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c > index 9964800c53c2..584af3b0a9e2 100644 > --- a/drivers/irqchip/irq-mscc-ocelot.c > +++ b/drivers/irqchip/irq-mscc-ocelot.c > @@ -44,6 +44,18 @@ static const struct chip_props ocelot_props = { > .n_irq = 24, > }; > > +static const struct chip_props serval_props = { > + .flags = FLAGS_HAS_TRIGGER, > + .reg_off_sticky = 0xc, > + .reg_off_ena = 0x14, > + .reg_off_ena_clr = 0x18, > + .reg_off_ena_set = 0x1c, > + .reg_off_ident = 0x20, > + .reg_off_trigger = 0x4, > + .reg_off_force = 0x8, > + .n_irq = 24, > +}; > + > static const struct chip_props luton_props = { > .flags = FLAGS_NEED_INIT_ENABLE | > FLAGS_FORCE_LUTON_STYLE, > @@ -210,6 +222,14 @@ static int __init ocelot_irq_init(struct device_node *node, > > IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init); > > +static int __init serval_irq_init(struct device_node *node, > + struct device_node *parent) > +{ > + return vcoreiii_irq_init(node, parent, &serval_props); > +} > + > +IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init); > + > static int __init luton_irq_init(struct device_node *node, > struct device_node *parent) > { > -- > 2.29.2 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT ` (3 preceding siblings ...) 2020-11-16 16:24 ` [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT @ 2020-11-16 16:24 ` Gregory CLEMENT 2020-11-18 10:46 ` Alexandre Belloni 4 siblings, 1 reply; 12+ messages in thread From: Gregory CLEMENT @ 2020-11-16 16:24 UTC (permalink / raw) To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT This patch extends irqchip driver for ocelot to be used with an other vcoreiii base platform: Jaguar2. Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index 584af3b0a9e2..0dfea8771172 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -70,6 +70,18 @@ static const struct chip_props luton_props = { .n_irq = 28, }; +static const struct chip_props jaguar2_props = { + .flags = FLAGS_HAS_TRIGGER, + .reg_off_sticky = 0x10, + .reg_off_ena = 0x18, + .reg_off_ena_clr = 0x1c, + .reg_off_ena_set = 0x20, + .reg_off_ident = 0x38, + .reg_off_trigger = 0x5c, + .reg_off_force = 0xc, + .n_irq = 29, +}; + static void ocelot_irq_unmask(struct irq_data *data) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); @@ -237,3 +249,11 @@ static int __init luton_irq_init(struct device_node *node, } IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); + +static int __init jaguar2_irq_init(struct device_node *node, + struct device_node *parent) +{ + return vcoreiii_irq_init(node, parent, &jaguar2_props); +} + +IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init); -- 2.29.2 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms 2020-11-16 16:24 ` [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT @ 2020-11-18 10:46 ` Alexandre Belloni 0 siblings, 0 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-11-18 10:46 UTC (permalink / raw) To: Gregory CLEMENT Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel, Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen, Steen.Hegelund On 16/11/2020 17:24:27+0100, Gregory CLEMENT wrote: > This patch extends irqchip driver for ocelot to be used with an other > vcoreiii base platform: Jaguar2. > > Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/irqchip/irq-mscc-ocelot.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c > index 584af3b0a9e2..0dfea8771172 100644 > --- a/drivers/irqchip/irq-mscc-ocelot.c > +++ b/drivers/irqchip/irq-mscc-ocelot.c > @@ -70,6 +70,18 @@ static const struct chip_props luton_props = { > .n_irq = 28, > }; > > +static const struct chip_props jaguar2_props = { > + .flags = FLAGS_HAS_TRIGGER, > + .reg_off_sticky = 0x10, > + .reg_off_ena = 0x18, > + .reg_off_ena_clr = 0x1c, > + .reg_off_ena_set = 0x20, > + .reg_off_ident = 0x38, > + .reg_off_trigger = 0x5c, > + .reg_off_force = 0xc, > + .n_irq = 29, > +}; > + > static void ocelot_irq_unmask(struct irq_data *data) > { > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); > @@ -237,3 +249,11 @@ static int __init luton_irq_init(struct device_node *node, > } > > IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); > + > +static int __init jaguar2_irq_init(struct device_node *node, > + struct device_node *parent) > +{ > + return vcoreiii_irq_init(node, parent, &jaguar2_props); > +} > + > +IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init); > -- > 2.29.2 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-11-18 20:51 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-11-16 16:24 [PATCH v3 0/5] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT 2020-11-16 16:24 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT 2020-11-18 20:50 ` Rob Herring 2020-11-16 16:24 ` [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT 2020-11-18 10:35 ` Alexandre Belloni 2020-11-16 16:24 ` [PATCH v3 3/5] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT 2020-11-18 10:45 ` Alexandre Belloni 2020-11-18 12:38 ` Marc Zyngier 2020-11-16 16:24 ` [PATCH v3 4/5] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT 2020-11-18 10:46 ` Alexandre Belloni 2020-11-16 16:24 ` [PATCH v3 5/5] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT 2020-11-18 10:46 ` Alexandre Belloni
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