* [PATCH v5 1/4] dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
2020-11-19 15:43 [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
@ 2020-11-19 15:43 ` Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 2/4] phy: ralink: Add PHY driver for " Sergio Paracuellos
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Sergio Paracuellos @ 2020-11-19 15:43 UTC (permalink / raw)
To: vkoul
Cc: robh+dt, kishon, gregkh, linux-kernel, devicetree, devel, neil,
Rob Herring
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
new file mode 100644
index 000000000000..cf32bbc45b5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek Mt7621 PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+properties:
+ compatible:
+ const: mediatek,mt7621-pci-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+ description: selects if the phy is dual-ported
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #phy-cells = <1>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v5 2/4] phy: ralink: Add PHY driver for MT7621 PCIe PHY
2020-11-19 15:43 [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 1/4] dt-bindings: phy: Add binding for Mediatek " Sergio Paracuellos
@ 2020-11-19 15:43 ` Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 3/4] MAINTAINERS: add MT7621 PHY PCI maintainer Sergio Paracuellos
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Sergio Paracuellos @ 2020-11-19 15:43 UTC (permalink / raw)
To: vkoul; +Cc: robh+dt, kishon, gregkh, linux-kernel, devicetree, devel, neil
This patch adds a driver for the PCIe PHY of MT7621 SoC.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/phy/ralink/Kconfig | 8 +
drivers/phy/ralink/Makefile | 1 +
drivers/phy/ralink/phy-mt7621-pci.c | 346 ++++++++++++++++++++++++++++
3 files changed, 355 insertions(+)
create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c
diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig
index da982c9cffb3..2fabb14d2998 100644
--- a/drivers/phy/ralink/Kconfig
+++ b/drivers/phy/ralink/Kconfig
@@ -2,6 +2,14 @@
#
# PHY drivers for Ralink platforms.
#
+config PHY_MT7621_PCI
+ tristate "MediaTek MT7621 PCI PHY Driver"
+ depends on (RALINK || COMPILE_TEST) && OF
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver,
+
config PHY_RALINK_USB
tristate "Ralink USB PHY driver"
depends on RALINK || COMPILE_TEST
diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
index d8d3ffcf0a15..cda2a4a7ca5e 100644
--- a/drivers/phy/ralink/Makefile
+++ b/drivers/phy/ralink/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o
obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c
new file mode 100644
index 000000000000..c452bc679d53
--- /dev/null
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Mediatek MT7621 PCI PHY Driver
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/sys_soc.h>
+#include <mt7621.h>
+#include <ralink_regs.h>
+
+#define RG_PE1_PIPE_REG 0x02c
+#define RG_PE1_PIPE_RST BIT(12)
+#define RG_PE1_PIPE_CMD_FRC BIT(4)
+
+#define RG_P0_TO_P1_WIDTH 0x100
+#define RG_PE1_H_LCDDS_REG 0x49c
+#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
+
+#define RG_PE1_FRC_H_XTAL_REG 0x400
+#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
+#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
+
+#define RG_PE1_FRC_PHY_REG 0x000
+#define RG_PE1_FRC_PHY_EN BIT(4)
+#define RG_PE1_PHY_EN BIT(5)
+
+#define RG_PE1_H_PLL_REG 0x490
+#define RG_PE1_H_PLL_BC GENMASK(23, 22)
+#define RG_PE1_H_PLL_BP GENMASK(21, 18)
+#define RG_PE1_H_PLL_IR GENMASK(15, 12)
+#define RG_PE1_H_PLL_IC GENMASK(11, 8)
+#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
+#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
+
+#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc
+#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
+
+#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
+#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
+
+#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
+#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
+
+#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
+#define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
+
+#define RG_PE1_H_PLL_BR_REG 0x4ac
+#define RG_PE1_H_PLL_BR GENMASK(18, 16)
+
+#define RG_PE1_MSTCKDIV_REG 0x414
+#define RG_PE1_MSTCKDIV GENMASK(7, 6)
+
+#define RG_PE1_FRC_MSTCKDIV BIT(5)
+
+#define XTAL_MODE_SEL_MASK 0x7
+
+#define MAX_PHYS 2
+
+/**
+ * struct mt7621_pci_phy - Mt7621 Pcie PHY core
+ * @dev: pointer to device
+ * @regmap: kernel regmap pointer
+ * @phy: pointer to the kernel PHY device
+ * @port_base: base register
+ * @has_dual_port: if the phy has dual ports.
+ * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
+ * needs to be executed. Depends on chip revision.
+ */
+struct mt7621_pci_phy {
+ struct device *dev;
+ struct regmap *regmap;
+ struct phy *phy;
+ void __iomem *port_base;
+ bool has_dual_port;
+ bool bypass_pipe_rst;
+};
+
+static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
+ u32 reg, u32 clr, u32 set)
+{
+ u32 val;
+
+ regmap_read(phy->regmap, reg, &val);
+
+ val &= ~clr;
+ val |= set;
+ regmap_write(phy->regmap, reg, val);
+}
+
+static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
+{
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
+
+ if (phy->has_dual_port) {
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
+ 0, RG_PE1_PIPE_RST);
+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
+ 0, RG_PE1_PIPE_CMD_FRC);
+ }
+}
+
+static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
+{
+ struct device *dev = phy->dev;
+ u32 xtal_mode;
+
+ xtal_mode = FIELD_GET(XTAL_MODE_SEL_MASK,
+ rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0));
+
+ /* Set PCIe Port PHY to disable SSC */
+ /* Debug Xtal Type */
+ mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
+ RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE,
+ FIELD_PREP(RG_PE1_FRC_H_XTAL_TYPE, 0x00));
+
+ /* disable port */
+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG, RG_PE1_PHY_EN,
+ RG_PE1_FRC_PHY_EN);
+
+ if (phy->has_dual_port) {
+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+ }
+
+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
+ /* Set Pre-divider ratio (for host mode) */
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,
+ FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01));
+
+ dev_dbg(dev, "Xtal is 40MHz\n");
+ } else if (xtal_mode >= 6) { /* 25MHz Xal */
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,
+ FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));
+
+ /* Select feedback clock */
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG,
+ RG_PE1_H_PLL_FBKSEL,
+ FIELD_PREP(RG_PE1_H_PLL_FBKSEL, 0x01));
+
+ /* DDS NCPO PCW (for host mode) */
+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
+ RG_PE1_H_LCDDS_SSC_PRD,
+ FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x00));
+
+ /* DDS SSC dither period control */
+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
+ RG_PE1_H_LCDDS_SSC_PRD,
+ FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x18d));
+
+ /* DDS SSC dither amplitude control */
+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG,
+ RG_PE1_H_LCDDS_SSC_DELTA |
+ RG_PE1_H_LCDDS_SSC_DELTA1,
+ FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA, 0x4a) |
+ FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA1, 0x4a));
+
+ dev_dbg(dev, "Xtal is 25MHz\n");
+ } else { /* 20MHz Xtal */
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV,
+ FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00));
+
+ dev_dbg(dev, "Xtal is 20MHz\n");
+ }
+
+ /* DDS clock inversion */
+ mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG,
+ RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV);
+
+ /* Set PLL bits */
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
+ RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
+ RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN,
+ FIELD_PREP(RG_PE1_H_PLL_BC, 0x02) |
+ FIELD_PREP(RG_PE1_H_PLL_BP, 0x06) |
+ FIELD_PREP(RG_PE1_H_PLL_IR, 0x02) |
+ FIELD_PREP(RG_PE1_H_PLL_IC, 0x01) |
+ FIELD_PREP(RG_PE1_PLL_DIVEN, 0x02));
+
+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
+ RG_PE1_H_PLL_BR, FIELD_PREP(RG_PE1_H_PLL_BR, 0x00));
+
+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
+ /* set force mode enable of da_pe1_mstckdiv */
+ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
+ RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
+ FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) |
+ RG_PE1_FRC_MSTCKDIV);
+ }
+}
+
+static int mt7621_pci_phy_init(struct phy *phy)
+{
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
+
+ if (mphy->bypass_pipe_rst)
+ mt7621_bypass_pipe_rst(mphy);
+
+ mt7621_set_phy_for_ssc(mphy);
+
+ return 0;
+}
+
+static int mt7621_pci_phy_power_on(struct phy *phy)
+{
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
+
+ /* Enable PHY and disable force mode */
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
+
+ if (mphy->has_dual_port) {
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
+ }
+
+ return 0;
+}
+
+static int mt7621_pci_phy_power_off(struct phy *phy)
+{
+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
+
+ /* Disable PHY */
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+
+ if (mphy->has_dual_port) {
+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
+ }
+
+ return 0;
+}
+
+static int mt7621_pci_phy_exit(struct phy *phy)
+{
+ return 0;
+}
+
+static const struct phy_ops mt7621_pci_phy_ops = {
+ .init = mt7621_pci_phy_init,
+ .exit = mt7621_pci_phy_exit,
+ .power_on = mt7621_pci_phy_power_on,
+ .power_off = mt7621_pci_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
+
+ if (WARN_ON(args->args[0] >= MAX_PHYS))
+ return ERR_PTR(-ENODEV);
+
+ mt7621_phy->has_dual_port = args->args[0];
+
+ dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
+ (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
+
+ return mt7621_phy->phy;
+}
+
+static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
+ { .soc_id = "mt7621", .revision = "E2" }
+};
+
+static const struct regmap_config mt7621_pci_phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x700,
+};
+
+static int mt7621_pci_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct soc_device_attribute *attr;
+ struct phy_provider *provider;
+ struct mt7621_pci_phy *phy;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ attr = soc_device_match(mt7621_pci_quirks_match);
+ if (attr)
+ phy->bypass_pipe_rst = true;
+
+ phy->dev = dev;
+ platform_set_drvdata(pdev, phy);
+
+ phy->port_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->port_base)) {
+ dev_err(dev, "failed to remap phy regs\n");
+ return PTR_ERR(phy->port_base);
+ }
+
+ phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
+ &mt7621_pci_phy_regmap_config);
+ if (IS_ERR(phy->regmap))
+ return PTR_ERR(phy->regmap);
+
+ phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_set_drvdata(phy->phy, phy);
+
+ provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id mt7621_pci_phy_ids[] = {
+ { .compatible = "mediatek,mt7621-pci-phy" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
+
+static struct platform_driver mt7621_pci_phy_driver = {
+ .probe = mt7621_pci_phy_probe,
+ .driver = {
+ .name = "mt7621-pci-phy",
+ .of_match_table = of_match_ptr(mt7621_pci_phy_ids),
+ },
+};
+
+builtin_platform_driver(mt7621_pci_phy_driver);
+
+MODULE_AUTHOR("Sergio Paracuellos <sergio.paracuellos@gmail.com>");
+MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v5 3/4] MAINTAINERS: add MT7621 PHY PCI maintainer
2020-11-19 15:43 [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 1/4] dt-bindings: phy: Add binding for Mediatek " Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 2/4] phy: ralink: Add PHY driver for " Sergio Paracuellos
@ 2020-11-19 15:43 ` Sergio Paracuellos
2020-11-19 15:43 ` [PATCH v5 4/4] staging: mt7621-pci-phy: remove driver from staging Sergio Paracuellos
2020-11-20 16:20 ` [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
4 siblings, 0 replies; 7+ messages in thread
From: Sergio Paracuellos @ 2020-11-19 15:43 UTC (permalink / raw)
To: vkoul; +Cc: robh+dt, kishon, gregkh, linux-kernel, devicetree, devel, neil
Adding myself as maintainer for mt7621 pci phy driver.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aefbbecfb266..31f808e58e73 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11100,6 +11100,12 @@ S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
F: drivers/i2c/busses/i2c-mt7621.c
+MEDIATEK MT7621 PHY PCI DRIVER
+M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
+F: drivers/phy/ralink/phy-mt7621-pci.c
+
MEDIATEK NAND CONTROLLER DRIVER
L: linux-mtd@lists.infradead.org
S: Orphan
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 4/4] staging: mt7621-pci-phy: remove driver from staging
2020-11-19 15:43 [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
` (2 preceding siblings ...)
2020-11-19 15:43 ` [PATCH v5 3/4] MAINTAINERS: add MT7621 PHY PCI maintainer Sergio Paracuellos
@ 2020-11-19 15:43 ` Sergio Paracuellos
2020-11-20 16:20 ` [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
4 siblings, 0 replies; 7+ messages in thread
From: Sergio Paracuellos @ 2020-11-19 15:43 UTC (permalink / raw)
To: vkoul; +Cc: robh+dt, kishon, gregkh, linux-kernel, devicetree, devel, neil
Remove this driver from staging because it has been moved
into its properly place in the kernel.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/mt7621-pci-phy/Kconfig | 8 -
drivers/staging/mt7621-pci-phy/Makefile | 2 -
drivers/staging/mt7621-pci-phy/TODO | 4 -
.../mediatek,mt7621-pci-phy.yaml | 36 --
.../staging/mt7621-pci-phy/pci-mt7621-phy.c | 373 ------------------
7 files changed, 426 deletions(-)
delete mode 100644 drivers/staging/mt7621-pci-phy/Kconfig
delete mode 100644 drivers/staging/mt7621-pci-phy/Makefile
delete mode 100644 drivers/staging/mt7621-pci-phy/TODO
delete mode 100644 drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml
delete mode 100644 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2d0310448eba..8a03ba56def5 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -94,8 +94,6 @@ source "drivers/staging/pi433/Kconfig"
source "drivers/staging/mt7621-pci/Kconfig"
-source "drivers/staging/mt7621-pci-phy/Kconfig"
-
source "drivers/staging/mt7621-pinctrl/Kconfig"
source "drivers/staging/mt7621-dma/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 757a892ab5b9..39319161301c 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_GREYBUS) += greybus/
obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
obj-$(CONFIG_PI433) += pi433/
obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
-obj-$(CONFIG_PCI_MT7621_PHY) += mt7621-pci-phy/
obj-$(CONFIG_PINCTRL_RT2880) += mt7621-pinctrl/
obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
diff --git a/drivers/staging/mt7621-pci-phy/Kconfig b/drivers/staging/mt7621-pci-phy/Kconfig
deleted file mode 100644
index 263e0a91c424..000000000000
--- a/drivers/staging/mt7621-pci-phy/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config PCI_MT7621_PHY
- tristate "MediaTek MT7621 PCI PHY Driver"
- depends on RALINK && OF
- select GENERIC_PHY
- help
- Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver,
-
diff --git a/drivers/staging/mt7621-pci-phy/Makefile b/drivers/staging/mt7621-pci-phy/Makefile
deleted file mode 100644
index b4d99b9119e0..000000000000
--- a/drivers/staging/mt7621-pci-phy/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_PCI_MT7621_PHY) += pci-mt7621-phy.o
diff --git a/drivers/staging/mt7621-pci-phy/TODO b/drivers/staging/mt7621-pci-phy/TODO
deleted file mode 100644
index a255e8f753eb..000000000000
--- a/drivers/staging/mt7621-pci-phy/TODO
+++ /dev/null
@@ -1,4 +0,0 @@
-
-- general code review and cleanup
-
-Cc: NeilBrown <neil@brown.name> and Sergio Paracuellos <sergio.paracuellos@gmail.com>
diff --git a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml
deleted file mode 100644
index cf32bbc45b5d..000000000000
--- a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-
-title: Mediatek Mt7621 PCIe PHY Device Tree Bindings
-
-maintainers:
- - Sergio Paracuellos <sergio.paracuellos@gmail.com>
-
-properties:
- compatible:
- const: mediatek,mt7621-pci-phy
-
- reg:
- maxItems: 1
-
- "#phy-cells":
- const: 1
- description: selects if the phy is dual-ported
-
-required:
- - compatible
- - reg
- - "#phy-cells"
-
-additionalProperties: false
-
-examples:
- - |
- pcie0_phy: pcie-phy@1e149000 {
- compatible = "mediatek,mt7621-pci-phy";
- reg = <0x1e149000 0x0700>;
- #phy-cells = <1>;
- };
diff --git a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
deleted file mode 100644
index 57743fd22be4..000000000000
--- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Mediatek MT7621 PCI PHY Driver
- * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/sys_soc.h>
-#include <mt7621.h>
-#include <ralink_regs.h>
-
-#define RG_PE1_PIPE_REG 0x02c
-#define RG_PE1_PIPE_RST BIT(12)
-#define RG_PE1_PIPE_CMD_FRC BIT(4)
-
-#define RG_P0_TO_P1_WIDTH 0x100
-#define RG_PE1_H_LCDDS_REG 0x49c
-#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
-#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
-
-#define RG_PE1_FRC_H_XTAL_REG 0x400
-#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
-#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
-#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
-
-#define RG_PE1_FRC_PHY_REG 0x000
-#define RG_PE1_FRC_PHY_EN BIT(4)
-#define RG_PE1_PHY_EN BIT(5)
-
-#define RG_PE1_H_PLL_REG 0x490
-#define RG_PE1_H_PLL_BC GENMASK(23, 22)
-#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
-#define RG_PE1_H_PLL_BP GENMASK(21, 18)
-#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
-#define RG_PE1_H_PLL_IR GENMASK(15, 12)
-#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
-#define RG_PE1_H_PLL_IC GENMASK(11, 8)
-#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
-#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
-#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
-#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
-#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1)
-
-#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc
-#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
-#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
-
-#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
-#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
-#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0xffff & (x)) << 0)
-
-#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
-#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)
-#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
-#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
-#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
-
-#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
-#define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
-
-#define RG_PE1_H_PLL_BR_REG 0x4ac
-#define RG_PE1_H_PLL_BR GENMASK(18, 16)
-#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
-
-#define RG_PE1_MSTCKDIV_REG 0x414
-#define RG_PE1_MSTCKDIV GENMASK(7, 6)
-#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
-
-#define RG_PE1_FRC_MSTCKDIV BIT(5)
-
-#define XTAL_MODE_SEL_SHIFT 6
-#define XTAL_MODE_SEL_MASK 0x7
-
-#define MAX_PHYS 2
-
-/**
- * struct mt7621_pci_phy - Mt7621 Pcie PHY core
- * @dev: pointer to device
- * @regmap: kernel regmap pointer
- * @phy: pointer to the kernel PHY device
- * @port_base: base register
- * @has_dual_port: if the phy has dual ports.
- * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
- * needs to be executed. Depends on chip revision.
- */
-struct mt7621_pci_phy {
- struct device *dev;
- struct regmap *regmap;
- struct phy *phy;
- void __iomem *port_base;
- bool has_dual_port;
- bool bypass_pipe_rst;
-};
-
-static inline u32 phy_read(struct mt7621_pci_phy *phy, u32 reg)
-{
- u32 val;
-
- regmap_read(phy->regmap, reg, &val);
-
- return val;
-}
-
-static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg)
-{
- regmap_write(phy->regmap, reg, val);
-}
-
-static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
- u32 reg, u32 clr, u32 set)
-{
- u32 val = phy_read(phy, reg);
-
- val &= ~clr;
- val |= set;
- phy_write(phy, val, reg);
-}
-
-static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
-{
- mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
- mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
-
- if (phy->has_dual_port) {
- mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
- 0, RG_PE1_PIPE_RST);
- mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
- 0, RG_PE1_PIPE_CMD_FRC);
- }
-}
-
-static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
-{
- struct device *dev = phy->dev;
- u32 xtal_mode;
-
- xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)
- >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
-
- /* Set PCIe Port PHY to disable SSC */
- /* Debug Xtal Type */
- mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
- RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE,
- RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
-
- /* disable port */
- mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG,
- RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
-
- if (phy->has_dual_port) {
- mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
- RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
- }
-
- if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
- /* Set Pre-divider ratio (for host mode) */
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
- RG_PE1_H_PLL_PREDIV,
- RG_PE1_H_PLL_PREDIV_VAL(0x01));
- dev_info(dev, "Xtal is 40MHz\n");
- } else if (xtal_mode >= 6) { /* 25MHz Xal */
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
- RG_PE1_H_PLL_PREDIV,
- RG_PE1_H_PLL_PREDIV_VAL(0x00));
- /* Select feedback clock */
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG,
- RG_PE1_H_PLL_FBKSEL,
- RG_PE1_H_PLL_FBKSEL_VAL(0x01));
- /* DDS NCPO PCW (for host mode) */
- mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
- RG_PE1_H_LCDDS_SSC_PRD,
- RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000));
- /* DDS SSC dither period control */
- mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
- RG_PE1_H_LCDDS_SSC_PRD,
- RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d));
- /* DDS SSC dither amplitude control */
- mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG,
- RG_PE1_H_LCDDS_SSC_DELTA |
- RG_PE1_H_LCDDS_SSC_DELTA1,
- RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a) |
- RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a));
- dev_info(dev, "Xtal is 25MHz\n");
- } else { /* 20MHz Xtal */
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
- RG_PE1_H_PLL_PREDIV,
- RG_PE1_H_PLL_PREDIV_VAL(0x00));
-
- dev_info(dev, "Xtal is 20MHz\n");
- }
-
- /* DDS clock inversion */
- mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG,
- RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV);
-
- /* Set PLL bits */
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
- RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
- RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN,
- RG_PE1_H_PLL_BC_VAL(0x02) | RG_PE1_H_PLL_BP_VAL(0x06) |
- RG_PE1_H_PLL_IR_VAL(0x02) | RG_PE1_H_PLL_IC_VAL(0x01) |
- RG_PE1_PLL_DIVEN_VAL(0x02));
-
- mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
- RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
-
- if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
- /* set force mode enable of da_pe1_mstckdiv */
- mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
- RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
- RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
- }
-}
-
-static int mt7621_pci_phy_init(struct phy *phy)
-{
- struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
-
- if (mphy->bypass_pipe_rst)
- mt7621_bypass_pipe_rst(mphy);
-
- mt7621_set_phy_for_ssc(mphy);
-
- return 0;
-}
-
-static int mt7621_pci_phy_power_on(struct phy *phy)
-{
- struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
-
- /* Enable PHY and disable force mode */
- mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
- RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
-
- if (mphy->has_dual_port) {
- mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
- RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
- }
-
- return 0;
-}
-
-static int mt7621_pci_phy_power_off(struct phy *phy)
-{
- struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
-
- /* Disable PHY */
- mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
- RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
-
- if (mphy->has_dual_port) {
- mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
- RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
- }
-
- return 0;
-}
-
-static int mt7621_pci_phy_exit(struct phy *phy)
-{
- return 0;
-}
-
-static const struct phy_ops mt7621_pci_phy_ops = {
- .init = mt7621_pci_phy_init,
- .exit = mt7621_pci_phy_exit,
- .power_on = mt7621_pci_phy_power_on,
- .power_off = mt7621_pci_phy_power_off,
- .owner = THIS_MODULE,
-};
-
-static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
- struct of_phandle_args *args)
-{
- struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
-
- if (WARN_ON(args->args[0] >= MAX_PHYS))
- return ERR_PTR(-ENODEV);
-
- mt7621_phy->has_dual_port = args->args[0];
-
- dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
- (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
-
- return mt7621_phy->phy;
-}
-
-static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
- { .soc_id = "mt7621", .revision = "E2" }
-};
-
-static const struct regmap_config mt7621_pci_phy_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = 0x700,
-};
-
-static int mt7621_pci_phy_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- const struct soc_device_attribute *attr;
- struct phy_provider *provider;
- struct mt7621_pci_phy *phy;
- struct resource *res;
-
- phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
- if (!phy)
- return -ENOMEM;
-
- attr = soc_device_match(mt7621_pci_quirks_match);
- if (attr)
- phy->bypass_pipe_rst = true;
-
- phy->dev = dev;
- platform_set_drvdata(pdev, phy);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(dev, "failed to get address resource\n");
- return -ENXIO;
- }
-
- phy->port_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(phy->port_base)) {
- dev_err(dev, "failed to remap phy regs\n");
- return PTR_ERR(phy->port_base);
- }
-
- phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
- &mt7621_pci_phy_regmap_config);
- if (IS_ERR(phy->regmap))
- return PTR_ERR(phy->regmap);
-
- phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
- if (IS_ERR(phy)) {
- dev_err(dev, "failed to create phy\n");
- return PTR_ERR(phy);
- }
-
- phy_set_drvdata(phy->phy, phy);
-
- provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
-
- return PTR_ERR_OR_ZERO(provider);
-}
-
-static const struct of_device_id mt7621_pci_phy_ids[] = {
- { .compatible = "mediatek,mt7621-pci-phy" },
- {},
-};
-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
-
-static struct platform_driver mt7621_pci_phy_driver = {
- .probe = mt7621_pci_phy_probe,
- .driver = {
- .name = "mt7621-pci-phy",
- .of_match_table = of_match_ptr(mt7621_pci_phy_ids),
- },
-};
-
-builtin_platform_driver(mt7621_pci_phy_driver);
-
-MODULE_AUTHOR("Sergio Paracuellos <sergio.paracuellos@gmail.com>");
-MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");
-MODULE_LICENSE("GPL v2");
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v5 0/4] MT7621 PCIe PHY
2020-11-19 15:43 [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
` (3 preceding siblings ...)
2020-11-19 15:43 ` [PATCH v5 4/4] staging: mt7621-pci-phy: remove driver from staging Sergio Paracuellos
@ 2020-11-20 16:20 ` Sergio Paracuellos
2020-11-21 12:10 ` Vinod Koul
4 siblings, 1 reply; 7+ messages in thread
From: Sergio Paracuellos @ 2020-11-20 16:20 UTC (permalink / raw)
To: vkoul
Cc: Rob Herring, Kishon Vijay Abraham I, Greg KH, linux-kernel,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, NeilBrown
Hi Vinod,
On Thu, Nov 19, 2020 at 4:43 PM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> This series adds support for the PCIe PHY found in the Mediatek
> MT7621 SoC.
>
> There is also a 'mt7621-pci' driver which is the controller part
> which is still in staging and is a client of this phy.
>
> Both drivers have been tested together in a gnubee1 board.
>
> This series are rebased on the top of linux-next:
> commit 4e78c578cb98 ("Add linux-next specific files for 20201030")
>
> Changes in v5:
> - PATCH 1/4: Recollect Rob's Reviewed-by of bindings.
> - PATCH 4/4: Recollect Greg's Acked-by for removing stuff from
> staging area.
> - Make Vinod's review comments changes in [0]:
> * Use FIELD_GET and FIELD_PREP apis and avoid multiple *_VAL and
> *_SHIFT custom definitions.
> * Remove phy-read and phy-write internal functions and directly
> call regmap_read and regmap_write in 'mt7621_phy_rmw'.
> * Change some traces from info to debug log level.
> * Note that I have maintained 'mt7621_phy_rmw' instead of use
> 'regmap_update_bits'. This is because in order to get a reliable
> boot registers must be written event the contained value in
> that register is the same. I have preferred doing in this way
> instead of using 'regmap_update_bits_base' passing 'false' for
> async and 'true' for the force write. If this way of using
> 'regmap_update_bits_base' is preferred just let me know.
I notice we already have 'regmap_write_bits' function. I will use this
and avoid mt7621_phy_rmw
and send v6 of this series.
Also, do you have any preference of where you want this series to be rebased on?
Best regards,
Sergio Paracuellos
>
> Changes in v4:
> - Bindings moved from txt to yaml so previous Rob's Reviewed-by
> is not in the new patch with the yaml file.
> - 'phy-cells' property means now if phy is dual-ported.
> - Avoid custom 'xlate' function and properly set registers
> when the phy is dual ported.
> - Add use of 'builtin_platform_driver'.
> - Added a patch including myself as maintainer in the
> MAINTAINERS file.
> - Add a patch removing patch from staging to make easier
> the complete inclusion and avoid possible problems might
> appear in 'linux-next' if the series are included.
>
> Changes in v3:
> - Recollect Rob's Reviewed-by of bindings.
> - Make Kishon Vijay suggested changes in v2:
> (See https://lkml.org/lkml/2019/4/17/53)
> - Kconfig:
> * Add depends on COMPILE_TEST
> * Select REGMAP_MMIO
> - Make use of 'soc_device_attribute' and 'soc_device_match'
> - Use regmap mmio API instead of directly 'readl' and 'writel'.
> - Use 'platform_get_resource' instead of 'of_address_to_resource'.
>
> Changes in v2:
> - Reorder patches to get bindings first in the series.
> - Don't use child nodes in the device tree. Use #phy-cells=1 instead.
> - Update driver code with new 'xlate' function for the new device tree.
> - Minor changes in driver's macros changing some spaces to tabs.
>
> Thanks in advance for your time.
>
> Best regards,
> Sergio Paracuellos
>
> [0]: http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2020-November/148864.html
>
> Sergio Paracuellos (4):
> dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
> phy: ralink: Add PHY driver for MT7621 PCIe PHY
> MAINTAINERS: add MT7621 PHY PCI maintainer
> staging: mt7621-pci-phy: remove driver from staging
>
> .../phy}/mediatek,mt7621-pci-phy.yaml | 0
> MAINTAINERS | 6 +
> drivers/phy/ralink/Kconfig | 8 ++
> drivers/phy/ralink/Makefile | 1 +
> .../ralink/phy-mt7621-pci.c} | 103 +++++++-----------
> drivers/staging/Kconfig | 2 -
> drivers/staging/Makefile | 1 -
> drivers/staging/mt7621-pci-phy/Kconfig | 8 --
> drivers/staging/mt7621-pci-phy/Makefile | 2 -
> drivers/staging/mt7621-pci-phy/TODO | 4 -
> 10 files changed, 53 insertions(+), 82 deletions(-)
> rename {drivers/staging/mt7621-pci-phy => Documentation/devicetree/bindings/phy}/mediatek,mt7621-pci-phy.yaml (100%)
> rename drivers/{staging/mt7621-pci-phy/pci-mt7621-phy.c => phy/ralink/phy-mt7621-pci.c} (76%)
> delete mode 100644 drivers/staging/mt7621-pci-phy/Kconfig
> delete mode 100644 drivers/staging/mt7621-pci-phy/Makefile
> delete mode 100644 drivers/staging/mt7621-pci-phy/TODO
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v5 0/4] MT7621 PCIe PHY
2020-11-20 16:20 ` [PATCH v5 0/4] MT7621 PCIe PHY Sergio Paracuellos
@ 2020-11-21 12:10 ` Vinod Koul
0 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2020-11-21 12:10 UTC (permalink / raw)
To: Sergio Paracuellos
Cc: Rob Herring, Kishon Vijay Abraham I, Greg KH, linux-kernel,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, NeilBrown
On 20-11-20, 17:20, Sergio Paracuellos wrote:
> Hi Vinod,
>
> On Thu, Nov 19, 2020 at 4:43 PM Sergio Paracuellos
> <sergio.paracuellos@gmail.com> wrote:
> >
> > This series adds support for the PCIe PHY found in the Mediatek
> > MT7621 SoC.
> >
> > There is also a 'mt7621-pci' driver which is the controller part
> > which is still in staging and is a client of this phy.
> >
> > Both drivers have been tested together in a gnubee1 board.
> >
> > This series are rebased on the top of linux-next:
> > commit 4e78c578cb98 ("Add linux-next specific files for 20201030")
> >
> > Changes in v5:
> > - PATCH 1/4: Recollect Rob's Reviewed-by of bindings.
> > - PATCH 4/4: Recollect Greg's Acked-by for removing stuff from
> > staging area.
> > - Make Vinod's review comments changes in [0]:
> > * Use FIELD_GET and FIELD_PREP apis and avoid multiple *_VAL and
> > *_SHIFT custom definitions.
> > * Remove phy-read and phy-write internal functions and directly
> > call regmap_read and regmap_write in 'mt7621_phy_rmw'.
> > * Change some traces from info to debug log level.
> > * Note that I have maintained 'mt7621_phy_rmw' instead of use
> > 'regmap_update_bits'. This is because in order to get a reliable
> > boot registers must be written event the contained value in
> > that register is the same. I have preferred doing in this way
> > instead of using 'regmap_update_bits_base' passing 'false' for
> > async and 'true' for the force write. If this way of using
> > 'regmap_update_bits_base' is preferred just let me know.
>
> I notice we already have 'regmap_write_bits' function. I will use this
> and avoid mt7621_phy_rmw
> and send v6 of this series.
>
> Also, do you have any preference of where you want this series to be rebased on?
Phy-next please
--
~Vinod
^ permalink raw reply [flat|nested] 7+ messages in thread