* [PATCH 1/3] drm/ingenic: Compute timings according to adjusted_mode->crtc_*
2020-11-19 15:55 [PATCH 0/3] drm/ingenic: Add support for delta-RGB panels Paul Cercueil
@ 2020-11-19 15:55 ` Paul Cercueil
2020-11-19 15:55 ` [PATCH 2/3] drm/ingenic: Properly compute timings when using a 3x8-bit panel Paul Cercueil
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2020-11-19 15:55 UTC (permalink / raw)
To: David Airlie, Daniel Vetter
Cc: Sam Ravnborg, od, dri-devel, linux-kernel, Paul Cercueil
The adjusted_mode->crtc_* fields contain the values adjusted for the
hardware, and are the ones that should be written to the registers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 368bfef8b340..998c63061fa8 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -190,15 +190,15 @@ static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
{
unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
- vpe = mode->vsync_end - mode->vsync_start;
- vds = mode->vtotal - mode->vsync_start;
- vde = vds + mode->vdisplay;
- vt = vde + mode->vsync_start - mode->vdisplay;
+ vpe = mode->crtc_vsync_end - mode->crtc_vsync_start;
+ vds = mode->crtc_vtotal - mode->crtc_vsync_start;
+ vde = vds + mode->crtc_vdisplay;
+ vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay;
- hpe = mode->hsync_end - mode->hsync_start;
- hds = mode->htotal - mode->hsync_start;
- hde = hds + mode->hdisplay;
- ht = hde + mode->hsync_start - mode->hdisplay;
+ hpe = mode->crtc_hsync_end - mode->crtc_hsync_start;
+ hds = mode->crtc_htotal - mode->crtc_hsync_start;
+ hde = hds + mode->crtc_hdisplay;
+ ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay;
regmap_write(priv->map, JZ_REG_LCD_VSYNC,
0 << JZ_LCD_VSYNC_VPS_OFFSET |
@@ -333,7 +333,7 @@ static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_pending_vblank_event *event = crtc_state->event;
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
- ingenic_drm_crtc_update_timings(priv, &crtc_state->mode);
+ ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode);
priv->update_clk_rate = true;
}
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] drm/ingenic: Properly compute timings when using a 3x8-bit panel
2020-11-19 15:55 [PATCH 0/3] drm/ingenic: Add support for delta-RGB panels Paul Cercueil
2020-11-19 15:55 ` [PATCH 1/3] drm/ingenic: Compute timings according to adjusted_mode->crtc_* Paul Cercueil
@ 2020-11-19 15:55 ` Paul Cercueil
2020-11-19 15:55 ` [PATCH 3/3] drm/ingenic: Add support for serial 8-bit delta-RGB panels Paul Cercueil
2020-11-29 21:59 ` [PATCH 0/3] drm/ingenic: Add support for " Sam Ravnborg
3 siblings, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2020-11-19 15:55 UTC (permalink / raw)
To: David Airlie, Daniel Vetter
Cc: Sam Ravnborg, od, dri-devel, linux-kernel, Paul Cercueil
The LCD controller expects timing values in dot-clock ticks, which is 3x
the timing values in pixels when using a 3x8-bit display; but it will
count the display area size in pixels either way. Go figure.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 998c63061fa8..0b2311b32b81 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -643,6 +643,7 @@ static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct drm_display_info *info = &conn_state->connector->display_info;
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
if (info->num_bus_formats != 1)
return -EINVAL;
@@ -651,10 +652,22 @@ static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
switch (*info->bus_formats) {
+ case MEDIA_BUS_FMT_RGB888_3X8:
+ /*
+ * The LCD controller expects timing values in dot-clock ticks,
+ * which is 3x the timing values in pixels when using a 3x8-bit
+ * display; but it will count the display area size in pixels
+ * either way. Go figure.
+ */
+ mode->crtc_clock = mode->clock * 3;
+ mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2;
+ mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2;
+ mode->crtc_hdisplay = mode->hdisplay;
+ mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2;
+ return 0;
case MEDIA_BUS_FMT_RGB565_1X16:
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RGB888_1X24:
- case MEDIA_BUS_FMT_RGB888_3X8:
return 0;
default:
return -EINVAL;
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] drm/ingenic: Add support for serial 8-bit delta-RGB panels
2020-11-19 15:55 [PATCH 0/3] drm/ingenic: Add support for delta-RGB panels Paul Cercueil
2020-11-19 15:55 ` [PATCH 1/3] drm/ingenic: Compute timings according to adjusted_mode->crtc_* Paul Cercueil
2020-11-19 15:55 ` [PATCH 2/3] drm/ingenic: Properly compute timings when using a 3x8-bit panel Paul Cercueil
@ 2020-11-19 15:55 ` Paul Cercueil
2020-11-29 21:59 ` [PATCH 0/3] drm/ingenic: Add support for " Sam Ravnborg
3 siblings, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2020-11-19 15:55 UTC (permalink / raw)
To: David Airlie, Daniel Vetter
Cc: Sam Ravnborg, od, dri-devel, linux-kernel, Paul Cercueil
Add support for 24-bit panels that are connected through a 8-bit bus and
use delta-RGB, which means a RGB pixel ordering on odd lines, and a GBR
pixel ordering on even lines.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 7 ++++++-
drivers/gpu/drm/ingenic/ingenic-drm.h | 14 ++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 0b2311b32b81..fdce8a8f276a 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -589,7 +589,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct drm_connector *conn = conn_state->connector;
struct drm_display_info *info = &conn->display_info;
- unsigned int cfg;
+ unsigned int cfg, rgbcfg = 0;
priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
@@ -626,6 +626,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
case MEDIA_BUS_FMT_RGB888_1X24:
cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
break;
+ case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
+ rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB;
+ fallthrough;
case MEDIA_BUS_FMT_RGB888_3X8:
cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
break;
@@ -636,6 +639,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
}
regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
+ regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg);
}
static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
@@ -653,6 +657,7 @@ static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
switch (*info->bus_formats) {
case MEDIA_BUS_FMT_RGB888_3X8:
+ case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
/*
* The LCD controller expects timing values in dot-clock ticks,
* which is 3x the timing values in pixels when using a 3x8-bit
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h b/drivers/gpu/drm/ingenic/ingenic-drm.h
index 9b48ce02803d..1b4347f7f084 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.h
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.h
@@ -31,6 +31,7 @@
#define JZ_REG_LCD_SA1 0x54
#define JZ_REG_LCD_FID1 0x58
#define JZ_REG_LCD_CMD1 0x5C
+#define JZ_REG_LCD_RGBC 0x90
#define JZ_REG_LCD_OSDC 0x100
#define JZ_REG_LCD_OSDCTRL 0x104
#define JZ_REG_LCD_OSDS 0x108
@@ -138,6 +139,19 @@
#define JZ_LCD_STATE_SOF_IRQ BIT(4)
#define JZ_LCD_STATE_DISABLED BIT(0)
+#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4)
+#define JZ_LCD_RGBC_ODD_RBG (0x1 << 4)
+#define JZ_LCD_RGBC_ODD_GRB (0x2 << 4)
+#define JZ_LCD_RGBC_ODD_GBR (0x3 << 4)
+#define JZ_LCD_RGBC_ODD_BRG (0x4 << 4)
+#define JZ_LCD_RGBC_ODD_BGR (0x5 << 4)
+#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0)
+#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0)
+#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0)
+#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0)
+#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0)
+#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0)
+
#define JZ_LCD_OSDC_OSDEN BIT(0)
#define JZ_LCD_OSDC_F0EN BIT(3)
#define JZ_LCD_OSDC_F1EN BIT(4)
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] drm/ingenic: Add support for delta-RGB panels
2020-11-19 15:55 [PATCH 0/3] drm/ingenic: Add support for delta-RGB panels Paul Cercueil
` (2 preceding siblings ...)
2020-11-19 15:55 ` [PATCH 3/3] drm/ingenic: Add support for serial 8-bit delta-RGB panels Paul Cercueil
@ 2020-11-29 21:59 ` Sam Ravnborg
3 siblings, 0 replies; 5+ messages in thread
From: Sam Ravnborg @ 2020-11-29 21:59 UTC (permalink / raw)
To: Paul Cercueil; +Cc: David Airlie, Daniel Vetter, od, linux-kernel, dri-devel
Hi Paul.
On Thu, Nov 19, 2020 at 03:55:56PM +0000, Paul Cercueil wrote:
> Hi,
>
> This patchset adds support for delta-RGB panels to the ingenic-drm
> driver. Delta-RGB panels have diamond-pattern subpixel layout, and
> expect odd lines to have RGB subpixel ordering, and even lines to have
> GBR subpixel ordering.
>
> Such panel is used in the YLM (aka. Anbernic) RG-99, RG-300, RG-280M
> and RG-280V handheld gaming consoles.
>
> Cheers,
> -Paul
>
> Paul Cercueil (3):
> drm/ingenic: Compute timings according to adjusted_mode->crtc_*
> drm/ingenic: Properly compute timings when using a 3x8-bit panel
> drm/ingenic: Add support for serial 8-bit delta-RGB panels
Strange panel, at least strange bit order.
Patches looks good and are all:
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
^ permalink raw reply [flat|nested] 5+ messages in thread