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From: Sia Jee Heng <jee.heng.sia@intel.com>
To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com, robh+dt@kernel.org
Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Date: Mon, 23 Nov 2020 10:34:51 +0800	[thread overview]
Message-ID: <20201123023452.7894-16-jee.heng.sia@intel.com> (raw)
In-Reply-To: <20201123023452.7894-1-jee.heng.sia@intel.com>

Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.

Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h          | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index dc7ddf98fd04..1a218fcdbb16 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
 #include <linux/device.h>
 #include <linux/dmaengine.h>
 #include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -1350,6 +1351,13 @@ static int dw_probe(struct platform_device *pdev)
 	dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
 	dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
 
+	/*
+	 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+	 * supported blocks is 1024. Device register width is 4 bytes.
+	 * Therefore, set constraint to 1024 * 4.
+	 */
+	dw->dma.dev->dma_parms = &dw->dma_parms;
+	dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
 	platform_set_drvdata(pdev, chip);
 
 	pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
 struct dw_axi_dma {
 	struct dma_device	dma;
 	struct dw_axi_dma_hcfg	*hdata;
+	struct device_dma_parameters	dma_parms;
 
 	/* channels */
 	struct axi_dma_chan	*chan;
-- 
2.18.0


  parent reply	other threads:[~2020-11-23  2:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-23  2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-30 22:25   ` Rob Herring
2020-12-09  3:21     ` Sia, Jee Heng
2020-12-10  1:22       ` Sia, Jee Heng
2020-11-23  2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-11-30 22:29   ` Rob Herring
2020-12-09  1:53     ` Sia, Jee Heng
2020-11-23  2:34 ` [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-11-23  2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-11-23  2:34 ` Sia Jee Heng [this message]
2020-11-23  2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
2020-11-23 10:22   ` Andy Shevchenko
2020-12-09  1:47     ` Sia, Jee Heng

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