From: Rob Herring <robh@kernel.org>
To: Sia Jee Heng <jee.heng.sia@intel.com>
Cc: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com,
andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Date: Mon, 30 Nov 2020 15:29:16 -0700 [thread overview]
Message-ID: <20201130222916.GA3146362@robh.at.kernel.org> (raw)
In-Reply-To: <20201123023452.7894-11-jee.heng.sia@intel.com>
On Mon, Nov 23, 2020 at 10:34:46AM +0800, Sia Jee Heng wrote:
> Add support for Intel KeemBay AxiDMA to the dw-axi-dmac
> Schemas DT binding.
>
> Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 6c2e8e612af5..9e3ca9083814 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller
>
> maintainers:
> - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
Also, for the first patch, missing a '>' on the end.
> + - Jee Heng Sia <jee.heng.sia@intel.com>
>
> description: |
> Synopsys DesignWare AXI DMA Controller DT Binding
> @@ -16,14 +17,18 @@ properties:
> compatible:
> enum:
> - snps,axi-dma-1.01a
> + - intel,kmb-axi-dma
>
> reg:
> + minItems: 1
> items:
> - description: Address range of the DMAC registers
> + - description: Address range of the DMAC APB registers
Nevermind for my 'reg' comment on the first patch.
>
> reg-names:
> items:
> - const: axidma_ctrl_regs
> + - const: axidma_apb_regs
>
> interrupts:
> maxItems: 1
> @@ -124,3 +129,25 @@ examples:
> snps,priority = <0 1 2 3>;
> snps,axi-max-burst-len = <16>;
> };
> +
> + - |
For what's just a new compatible and extra reg field, I don't think we
need another example.
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + /* example with intel,kmb-axi-dma */
> + #define KEEM_BAY_PSS_AXI_DMA
> + #define KEEM_BAY_PSS_APB_AXI_DMA
> + axi_dma: dma@28000000 {
> + compatible = "intel,kmb-axi-dma";
> + reg = <0x28000000 0x1000>, <0x20250000 0x24>;
> + reg-names = "axidma_ctrl_regs", "axidma_apb_regs";
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core-clk", "cfgr-clk";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AXI_DMA>, <&scmi_clk KEEM_BAY_PSS_APB_AXI_DMA>;
> + #dma-cells = <1>;
> + dma-channels = <8>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,priority = <0 0 0 0 0 0 0 0>;
> + snps,block-size = <1024 1024 1024 1024 1024 1024 1024 1024>;
> + snps,axi-max-burst-len = <16>;
> + };
> --
> 2.18.0
>
next prev parent reply other threads:[~2020-11-30 22:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-30 22:25 ` Rob Herring
2020-12-09 3:21 ` Sia, Jee Heng
2020-12-10 1:22 ` Sia, Jee Heng
2020-11-23 2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-11-30 22:29 ` Rob Herring [this message]
2020-12-09 1:53 ` Sia, Jee Heng
2020-11-23 2:34 ` [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
2020-11-23 10:22 ` Andy Shevchenko
2020-12-09 1:47 ` Sia, Jee Heng
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