* [PATCH 1/3] arm64: dts: mt8183: Add dsi node
2020-11-27 10:49 [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Enric Balletbo i Serra
@ 2020-11-27 10:49 ` Enric Balletbo i Serra
2020-11-27 10:49 ` [PATCH 2/3] arm64: dts: mt8183: Add iommu and larb nodes Enric Balletbo i Serra
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Enric Balletbo i Serra @ 2020-11-27 10:49 UTC (permalink / raw)
To: linux-kernel
Cc: Collabora Kernel ML, Jitao Shi, Matthias Brugger, Rob Herring,
devicetree, linux-arm-kernel, linux-mediatek
From: Jitao Shi <jitao.shi@mediatek.com>
Add dsi and mipitx nodes to the MT8183.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 31 ++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7839480df075..da7212e21fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -892,10 +892,27 @@ mmc1: mmc@11240000 {
status = "disabled";
};
+ mipi_tx0: mipi-dphy@11e50000 {
+ compatible = "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11e50000 0 0x1000>;
+ clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ nvmem-cells = <&mipi_tx_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
efuse: efuse@11f10000 {
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mipi_tx_calibration: calib@190 {
+ reg = <0x190 0xc>;
+ };
};
u3phy: usb-phy@11f40000 {
@@ -937,6 +954,20 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ mediatek,syscon-dsi = <&mmsys 0x140>;
+ clocks = <&mmsys CLK_MM_DSI0_MM>,
+ <&mmsys CLK_MM_DSI0_IF>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ };
+
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
--
2.29.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] arm64: dts: mt8183: Add iommu and larb nodes
2020-11-27 10:49 [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Enric Balletbo i Serra
2020-11-27 10:49 ` [PATCH 1/3] arm64: dts: mt8183: Add dsi node Enric Balletbo i Serra
@ 2020-11-27 10:49 ` Enric Balletbo i Serra
2020-11-27 10:49 ` [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183 Enric Balletbo i Serra
2020-11-27 11:23 ` [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Matthias Brugger
3 siblings, 0 replies; 6+ messages in thread
From: Enric Balletbo i Serra @ 2020-11-27 10:49 UTC (permalink / raw)
To: linux-kernel
Cc: Collabora Kernel ML, Matthias Brugger, Rob Herring, devicetree,
linux-arm-kernel, linux-mediatek
Add iommu and larb nodes to the MT8183.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 ++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index da7212e21fdf..ba9ff192cda3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
@@ -521,6 +522,15 @@ systimer: timer@10017000 {
clock-names = "clk13m";
};
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt8183-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
+ &larb4 &larb5 &larb6>;
+ #iommu-cells = <1>;
+ };
+
gce: mailbox@10238000 {
compatible = "mediatek,mt8183-gce";
reg = <0 0x10238000 0 0x4000>;
@@ -968,6 +978,16 @@ dsi0: dsi@14014000 {
phy-names = "dphy";
};
+ larb0: larb@14017000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x14017000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clock-names = "apb", "smi";
+ };
+
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
@@ -984,18 +1004,57 @@ imgsys: syscon@15020000 {
#clock-cells = <1>;
};
+ larb5: larb@15021000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x15021000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
+ <&mmsys CLK_MM_GALS_IMG2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
+ };
+
+ larb2: larb@1502f000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1502f000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
+ <&mmsys CLK_MM_GALS_IPU2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8183-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
+ };
+
vencsys: syscon@17000000 {
compatible = "mediatek,mt8183-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@17010000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_LARB>,
+ <&vencsys CLK_VENC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
+ };
+
ipu_conn: syscon@19000000 {
compatible = "mediatek,mt8183-ipu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;
@@ -1025,5 +1084,25 @@ camsys: syscon@1a000000 {
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb6: larb@1a001000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
+ <&mmsys CLK_MM_GALS_CAM2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
+ };
+
+ larb3: larb@1a002000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
+ <&mmsys CLK_MM_GALS_IPU12MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
+ };
};
};
--
2.29.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183
2020-11-27 10:49 [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Enric Balletbo i Serra
2020-11-27 10:49 ` [PATCH 1/3] arm64: dts: mt8183: Add dsi node Enric Balletbo i Serra
2020-11-27 10:49 ` [PATCH 2/3] arm64: dts: mt8183: Add iommu and larb nodes Enric Balletbo i Serra
@ 2020-11-27 10:49 ` Enric Balletbo i Serra
2020-12-10 7:01 ` CK Hu
2020-11-27 11:23 ` [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Matthias Brugger
3 siblings, 1 reply; 6+ messages in thread
From: Enric Balletbo i Serra @ 2020-11-27 10:49 UTC (permalink / raw)
To: linux-kernel
Cc: Collabora Kernel ML, Matthias Brugger, Rob Herring, devicetree,
linux-arm-kernel, linux-mediatek
Add display subsystem device nodes to allow video output.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++
1 file changed, 114 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index ba9ff192cda3..34d83f517b07 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
@@ -33,6 +34,11 @@ aliases {
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
+ ovl0 = &ovl0;
+ ovl-2l0 = &ovl_2l0;
+ ovl-2l1 = &ovl_2l1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
};
cpus {
@@ -964,6 +970,107 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
+ ovl0: ovl@14008000 {
+ compatible = "mediatek,mt8183-disp-ovl";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
+ };
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+
+ ovl_2l1: ovl@1400a000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+ iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+ };
+
+ rdma0: rdma@1400b000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma_fifo_size = <5120>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ };
+
+ rdma1: rdma@1400c000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma_fifo_size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
+ color0: color@1400e000 {
+ compatible = "mediatek,mt8183-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@14010000 {
+ compatible = "mediatek,mt8183-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@14011000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi";
reg = <0 0x14014000 0 0x1000>;
@@ -978,6 +1085,13 @@ dsi0: dsi@14014000 {
phy-names = "dphy";
};
+ mutex: mutex@14016000 {
+ compatible = "mediatek,mt8183-disp-mutex";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ };
+
larb0: larb@14017000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x14017000 0 0x1000>;
--
2.29.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183
2020-11-27 10:49 ` [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183 Enric Balletbo i Serra
@ 2020-12-10 7:01 ` CK Hu
0 siblings, 0 replies; 6+ messages in thread
From: CK Hu @ 2020-12-10 7:01 UTC (permalink / raw)
To: Enric Balletbo i Serra
Cc: linux-kernel, devicetree, Rob Herring, linux-mediatek,
Matthias Brugger, Collabora Kernel ML, linux-arm-kernel
Hi, Enric:
On Fri, 2020-11-27 at 11:49 +0100, Enric Balletbo i Serra wrote:
> Add display subsystem device nodes to allow video output.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++
> 1 file changed, 114 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index ba9ff192cda3..34d83f517b07 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -6,6 +6,7 @@
> */
>
> #include <dt-bindings/clock/mt8183-clk.h>
> +#include <dt-bindings/gce/mt8173-gce.h>
This should be
#include <dt-bindings/gce/mt8183-gce.h>
Regards,
CK
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/memory/mt8183-larb-port.h>
> @@ -33,6 +34,11 @@ aliases {
> i2c9 = &i2c9;
> i2c10 = &i2c10;
> i2c11 = &i2c11;
> + ovl0 = &ovl0;
> + ovl-2l0 = &ovl_2l0;
> + ovl-2l1 = &ovl_2l1;
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> };
>
> cpus {
> @@ -964,6 +970,107 @@ mmsys: syscon@14000000 {
> #clock-cells = <1>;
> };
>
> + ovl0: ovl@14008000 {
> + compatible = "mediatek,mt8183-disp-ovl";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu M4U_PORT_DISP_OVL0>;
> + mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14009000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> + mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> + };
> +
> + ovl_2l1: ovl@1400a000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
> + mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + rdma0: rdma@1400b000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma_fifo_size = <5120>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + rdma1: rdma@1400c000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma_fifo_size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> + };
> +
> + color0: color@1400e000 {
> + compatible = "mediatek,mt8183-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400f000 {
> + compatible = "mediatek,mt8183-disp-ccorr";
> + reg = <0 0x1400f000 0 0x1000>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@14010000 {
> + compatible = "mediatek,mt8183-disp-aal",
> + "mediatek,mt8173-disp-aal";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + };
> +
> + gamma0: gamma@14011000 {
> + compatible = "mediatek,mt8183-disp-gamma",
> + "mediatek,mt8173-disp-gamma";
> + reg = <0 0x14011000 0 0x1000>;
> + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + };
> +
> + dither0: dither@14012000 {
> + compatible = "mediatek,mt8183-disp-dither";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + };
> +
> dsi0: dsi@14014000 {
> compatible = "mediatek,mt8183-dsi";
> reg = <0 0x14014000 0 0x1000>;
> @@ -978,6 +1085,13 @@ dsi0: dsi@14014000 {
> phy-names = "dphy";
> };
>
> + mutex: mutex@14016000 {
> + compatible = "mediatek,mt8183-disp-mutex";
> + reg = <0 0x14016000 0 0x1000>;
> + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + };
> +
> larb0: larb@14017000 {
> compatible = "mediatek,mt8183-smi-larb";
> reg = <0 0x14017000 0 0x1000>;
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards
2020-11-27 10:49 [PATCH 0/3] arm64: dts: mediatek: Add dsi and display support for MT8183 based boards Enric Balletbo i Serra
` (2 preceding siblings ...)
2020-11-27 10:49 ` [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183 Enric Balletbo i Serra
@ 2020-11-27 11:23 ` Matthias Brugger
3 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2020-11-27 11:23 UTC (permalink / raw)
To: Enric Balletbo i Serra, linux-kernel
Cc: Collabora Kernel ML, Rob Herring, devicetree, linux-arm-kernel,
linux-mediatek
On 27/11/2020 11:49, Enric Balletbo i Serra wrote:
> Dear all,
>
> The following patches add the required nodes to enable dsi and display
> support for MT8183 based boards. The patches were tested on a Lenovo
> Ideapad Duet with an out-of-tree patch that enables the display for that
> board.
Applied to v5.10-next/dts64
Thanks!
>
> The patches depends on [1].
>
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
>
> Enric Balletbo i Serra (2):
> arm64: dts: mt8183: Add iommu and larb nodes
> arm64: dts: mt8183: Add display nodes for MT8183
>
> Jitao Shi (1):
> arm64: dts: mt8183: Add dsi node
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 224 +++++++++++++++++++++++
> 1 file changed, 224 insertions(+)
>
^ permalink raw reply [flat|nested] 6+ messages in thread