From: Andrew Lunn <andrew@lunn.ch>
To: Lukasz Majewski <lukma@denx.de>
Cc: Vladimir Oltean <olteanv@gmail.com>,
Fugang Duan <fugang.duan@nxp.com>,
"David S . Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
netdev@vger.kernel.org, Fabio Estevam <festevam@gmail.com>,
Vivien Didelot <vivien.didelot@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Florian Fainelli <f.fainelli@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>,
stefan.agner@toradex.com, krzk@kernel.org,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [RFC 0/4] net: l2switch: Provide support for L2 switch on i.MX28 SoC
Date: Fri, 27 Nov 2020 16:10:22 +0100 [thread overview]
Message-ID: <20201127151022.GQ2073444@lunn.ch> (raw)
In-Reply-To: <20201127102528.33737ea4@jawa>
On Fri, Nov 27, 2020 at 10:25:28AM +0100, Lukasz Majewski wrote:
> Hi Andrew,
>
> > > > I would push back and say that the switch offers bridge
> > > > acceleration for the FEC.
> > >
> > > Am I correct, that the "bridge acceleration" means in-hardware
> > > support for L2 packet bridging?
> >
> > You should think of the hardware as an accelerator, not a switch. The
> > hardware is there to accelerate what linux can already do. You setup a
> > software bridge in linux, and then offload L2 switching to the
> > accelerator. You setup vlans in linux, and then offload the filtering
> > of them to the accelerator. If there is something linux can do, but
> > the hardware cannot accelerate, you leave linux to do it in software.
>
> Ok.
>
> >
> > > Do you propose to catch some kind of notification when user calls:
> > >
> > > ip link add name br0 type bridge; ip link set br0 up;
> > > ip link set lan1 up; ip link set lan2 up;
> > > ip link set lan1 master br0; ip link set lan2 master br0;
> > > bridge link
> > >
> > > And then configure the FEC driver to use this L2 switch driver?
> >
> > That is what switchdev does. There are various hooks in the network
> > stack which call into switchdev to ask it to offload operations to the
> > accelerator.
>
> Ok.
>
> >
> > > The differences from "normal" DSA switches:
> > >
> > > 1. It uses mapped memory (for its register space) for
> > > configuration/statistics gathering (instead of e.g. SPI, I2C)
> Hmm...
>
> I cannot find such chapter in the official documentation from NXP:
> "VFxxx Controller Reference Manual, Rev. 0, 10/2016"
I have
Vybrid Reference Manual
F-Series
Document Number: VYBRIDRM
Rev 7, 06/2014
Andrew
next prev parent reply other threads:[~2020-11-27 15:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 23:24 [RFC 0/4] net: l2switch: Provide support for L2 switch on i.MX28 SoC Lukasz Majewski
2020-11-25 23:24 ` [RFC 1/4] net: fec: Move some defines to ./drivers/net/ethernet/freescale/fec.h header Lukasz Majewski
2020-11-25 23:24 ` [RFC 2/4] net: dsa: Provide DSA driver for NXP's More Than IP L2 switch Lukasz Majewski
2020-11-25 23:24 ` [RFC 3/4] net: imx: l2switch: Adjust fec_main.c to provide support for " Lukasz Majewski
2020-11-25 23:24 ` [RFC 4/4] ARM: dts: imx28: Add description for L2 switch on XEA board Lukasz Majewski
2020-11-26 0:00 ` [RFC 0/4] net: l2switch: Provide support for L2 switch on i.MX28 SoC Andrew Lunn
2020-11-26 1:30 ` Florian Fainelli
2020-11-26 3:10 ` Andrew Lunn
2020-11-26 10:10 ` Lukasz Majewski
2020-11-26 14:45 ` Andrew Lunn
2020-11-27 0:03 ` Lukasz Majewski
2020-11-26 12:30 ` Vladimir Oltean
2020-11-26 23:35 ` Lukasz Majewski
2020-11-27 0:55 ` Andrew Lunn
2020-11-27 9:16 ` Lukasz Majewski
2020-11-27 1:08 ` Andrew Lunn
2020-11-27 9:25 ` Lukasz Majewski
2020-11-27 15:10 ` Andrew Lunn [this message]
2021-06-17 11:08 ` Lukasz Majewski
2021-06-17 13:57 ` Andrew Lunn
2020-11-27 19:29 ` Vladimir Oltean
2020-11-28 0:33 ` Lukasz Majewski
2020-11-28 4:34 ` Florian Fainelli
2020-11-29 21:59 ` Lukasz Majewski
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