[PATCH v2 0/3] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it

[PATCH v2 0/3] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it

[Pratyush Yadav]

Hi,

The Cypress Semper S28 flash family uses 2-bit ECC by default. Under
this ECC scheme, multi-pass page programs result in a program error.
This means that unlike many other SPI NOR flashes, bit-walking cannot be
done. In other words, once a page is programmed, its bits cannot then be
flipped to 0 without an erase in between.

This causes problems with UBIFS because it uses bit-walking to clear EC
and VID magic numbers from a PEB before issuing an erase to preserve the
file system correctness in case of power cuts.

This series fixes that by setting mtd->writesize to the ECC block size
(16) and making sure UBIFS does not try to do a multi-pass write on
flashes with writesize > 1.

It is based on the xSPI/8D series that adds support for Cypress S28
flash [0] (it is in next now). The patches themselves are independent of
that series in the sense that they don't rely on 8D support. But since
S28 flash is not supported without that series, these patches don't make
much sense without it.

Tested on Cypress S28HS512T and MT35XU512ABA on J7200 and J721E
respectively.

[0] https://lore.kernel.org/linux-mtd/20201005153138.6437-1-p.yadav@ti.com/

Pratyush Yadav (3):
  UBI: Do not zero out EC and VID on ECC-ed NOR flashes
  mtd: spi-nor: core: Allow flashes to specify MTD writesize
  mtd: spi-nor: spansion: Set ECC block size

 drivers/mtd/spi-nor/core.c     | 4 +++-
 drivers/mtd/spi-nor/core.h     | 3 +++
 drivers/mtd/spi-nor/spansion.c | 1 +
 drivers/mtd/ubi/build.c        | 4 +---
 drivers/mtd/ubi/io.c           | 9 ++++++++-
 5 files changed, 16 insertions(+), 5 deletions(-)

--
2.28.0

[PATCH v2 1/3] UBI: Do not zero out EC and VID on ECC-ed NOR flashes

[Pratyush Yadav]

For NOR flashes EC and VID are zeroed out before an erase is issued to
make sure UBI does not mistakenly treat the PEB as used and associate it
with an LEB.

But on some flashes, like the Cypress Semper S28 SPI NOR flash family,
multi-pass page programming is not allowed on the default ECC scheme.
This means zeroing out these magic numbers will result in the flash
throwing a page programming error.

Do not zero out EC and VID for such flashes. A writesize > 1 is an
indication of an ECC-ed flash.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---

Notes:
    Changes in v2:
    
    - Use mtd->writesize to check if multi-pass programming can be done
      instead of using MTD_NO_MULTI_PASS_WRITE.
    - Remove the assertion that a NOR flash most have writesize of 1.

 drivers/mtd/ubi/build.c | 4 +---
 drivers/mtd/ubi/io.c    | 9 ++++++++-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index e85b04e9716b..25fd7816b1f4 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -628,10 +628,8 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024)
 		ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024);
 	}
 
-	if (ubi->mtd->type == MTD_NORFLASH) {
-		ubi_assert(ubi->mtd->writesize == 1);
+	if (ubi->mtd->type == MTD_NORFLASH)
 		ubi->nor_flash = 1;
-	}
 
 	ubi->min_io_size = ubi->mtd->writesize;
 	ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft;
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 14d890b00d2c..2f3312c31e51 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -535,7 +535,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture)
 		return -EROFS;
 	}
 
-	if (ubi->nor_flash) {
+	/*
+	 * If the flash is ECC-ed then we have to erase the ECC block before we
+	 * can write to it. But the write is in preparation to an erase in the
+	 * first place. This means we cannot zero out EC and VID before the
+	 * erase and we just have to hope the flash starts erasing from the
+	 * start of the page.
+	 */
+	if (ubi->nor_flash && ubi->mtd->writesize == 1) {
 		err = nor_erase_prepare(ubi, pnum);
 		if (err)
 			return err;
-- 
2.28.0

[PATCH v2 2/3] mtd: spi-nor: core: Allow flashes to specify MTD writesize

[Pratyush Yadav]

Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
multi-pass writes to an ECC block is not allowed. In other words, once
data is programmed to an ECC block, it can't be programmed again without
erasing it first.

Upper layers like file systems need to be given this information so they
do not cause error conditions on the flash by attempting multi-pass
programming. This can be done by setting 'writesize' in 'struct
mtd_info'.

Set the default to 1 but allow flashes to modify it in fixup hooks. If
more flashes show up with this constraint in the future it might be
worth it to add it to 'struct flash_info', but for now increasing its
size is not worth it.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---

Notes:
    New in v2.

 drivers/mtd/spi-nor/core.c | 4 +++-
 drivers/mtd/spi-nor/core.h | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 5bee7c8da4dc..80fbcb9c0828 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3054,6 +3054,8 @@ static int spi_nor_init_params(struct spi_nor *nor)
 	if (!nor->params)
 		return -ENOMEM;
 
+	nor->params->writesize = 1;
+
 	spi_nor_info_init_params(nor);
 
 	spi_nor_manufacturer_init_params(nor);
@@ -3430,7 +3432,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
 		mtd->name = dev_name(dev);
 	mtd->priv = nor;
 	mtd->type = MTD_NORFLASH;
-	mtd->writesize = 1;
+	mtd->writesize = nor->params->writesize;
 	mtd->flags = MTD_CAP_NORFLASH;
 	mtd->size = nor->params->size;
 	mtd->_erase = spi_nor_erase;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 0a775a7b5606..413ea311e632 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -197,6 +197,8 @@ struct spi_nor_locking_ops {
  * @rdsr_dummy:		dummy cycles needed for Read Status Register command.
  * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status Register
  *			command.
+ * @writesize		Minimal writable flash unit size. Defaults to 1. Set to
+ *			ECC unit size for ECC-ed flashes.
  * @hwcaps:		describes the read and page program hardware
  *			capabilities.
  * @reads:		read capabilities ordered by priority: the higher index
@@ -222,6 +224,7 @@ struct spi_nor_flash_parameter {
 	u32				page_size;
 	u8				rdsr_dummy;
 	u8				rdsr_addr_nbytes;
+	u32				writesize;
 
 	struct spi_nor_hwcaps		hwcaps;
 	struct spi_nor_read_command	reads[SNOR_CMD_READ_MAX];
-- 
2.28.0

[PATCH v2 3/3] mtd: spi-nor: spansion: Set ECC block size

[Pratyush Yadav]

The S28 flash family uses 2-bit ECC by default with each ECC block being
16 bytes. Under this scheme multi-pass programming to an ECC block is
not allowed. Set the writesize to make sure multi-pass programming is
not attempted on the flash.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---

Notes:
    New in v2.

 drivers/mtd/spi-nor/spansion.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index e487fd341a56..b0c5521c1e27 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -109,6 +109,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
 static void s28hs512t_default_init(struct spi_nor *nor)
 {
 	nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
+	nor->params->writesize = 16;
 }
 
 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
-- 
2.28.0

Re: [PATCH v2 0/3] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it

[Pratyush Yadav]

Hi,

On 18/11/20 11:54PM, Pratyush Yadav wrote:
> Hi,
> 
> The Cypress Semper S28 flash family uses 2-bit ECC by default. Under
> this ECC scheme, multi-pass page programs result in a program error.
> This means that unlike many other SPI NOR flashes, bit-walking cannot be
> done. In other words, once a page is programmed, its bits cannot then be
> flipped to 0 without an erase in between.
> 
> This causes problems with UBIFS because it uses bit-walking to clear EC
> and VID magic numbers from a PEB before issuing an erase to preserve the
> file system correctness in case of power cuts.
> 
> This series fixes that by setting mtd->writesize to the ECC block size
> (16) and making sure UBIFS does not try to do a multi-pass write on
> flashes with writesize > 1.
> 
> It is based on the xSPI/8D series that adds support for Cypress S28
> flash [0] (it is in next now). The patches themselves are independent of
> that series in the sense that they don't rely on 8D support. But since
> S28 flash is not supported without that series, these patches don't make
> much sense without it.
> 
> Tested on Cypress S28HS512T and MT35XU512ABA on J7200 and J721E
> respectively.
> 
> [0] https://lore.kernel.org/linux-mtd/20201005153138.6437-1-p.yadav@ti.com/

Any comments on the series? If not, can it be picked up?
 
> Pratyush Yadav (3):
>   UBI: Do not zero out EC and VID on ECC-ed NOR flashes
>   mtd: spi-nor: core: Allow flashes to specify MTD writesize
>   mtd: spi-nor: spansion: Set ECC block size
> 
>  drivers/mtd/spi-nor/core.c     | 4 +++-
>  drivers/mtd/spi-nor/core.h     | 3 +++
>  drivers/mtd/spi-nor/spansion.c | 1 +
>  drivers/mtd/ubi/build.c        | 4 +---
>  drivers/mtd/ubi/io.c           | 9 ++++++++-
>  5 files changed, 16 insertions(+), 5 deletions(-)
> 
> --
> 2.28.0
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments India

Re: [PATCH v2 0/3] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it

[Richard Weinberger]

On Tue, Nov 24, 2020 at 2:58 PM Pratyush Yadav <p.yadav@ti.com> wrote:
>
> Hi,
>
> On 18/11/20 11:54PM, Pratyush Yadav wrote:
> > Hi,
> >
> > The Cypress Semper S28 flash family uses 2-bit ECC by default. Under
> > this ECC scheme, multi-pass page programs result in a program error.
> > This means that unlike many other SPI NOR flashes, bit-walking cannot be
> > done. In other words, once a page is programmed, its bits cannot then be
> > flipped to 0 without an erase in between.
> >
> > This causes problems with UBIFS because it uses bit-walking to clear EC
> > and VID magic numbers from a PEB before issuing an erase to preserve the
> > file system correctness in case of power cuts.
> >
> > This series fixes that by setting mtd->writesize to the ECC block size
> > (16) and making sure UBIFS does not try to do a multi-pass write on
> > flashes with writesize > 1.
> >
> > It is based on the xSPI/8D series that adds support for Cypress S28
> > flash [0] (it is in next now). The patches themselves are independent of
> > that series in the sense that they don't rely on 8D support. But since
> > S28 flash is not supported without that series, these patches don't make
> > much sense without it.
> >
> > Tested on Cypress S28HS512T and MT35XU512ABA on J7200 and J721E
> > respectively.
> >
> > [0] https://lore.kernel.org/linux-mtd/20201005153138.6437-1-p.yadav@ti.com/
>
> Any comments on the series? If not, can it be picked up?
>
> > Pratyush Yadav (3):
> >   UBI: Do not zero out EC and VID on ECC-ed NOR flashes
> >   mtd: spi-nor: core: Allow flashes to specify MTD writesize
> >   mtd: spi-nor: spansion: Set ECC block size
> >
> >  drivers/mtd/spi-nor/core.c     | 4 +++-
> >  drivers/mtd/spi-nor/core.h     | 3 +++
> >  drivers/mtd/spi-nor/spansion.c | 1 +
> >  drivers/mtd/ubi/build.c        | 4 +---
> >  drivers/mtd/ubi/io.c           | 9 ++++++++-
> >  5 files changed, 16 insertions(+), 5 deletions(-)

Can we please have am ACK from NOR folks? :-)

-- 
Thanks,
//richard

Re: [PATCH v2 1/3] UBI: Do not zero out EC and VID on ECC-ed NOR flashes

[Tudor.Ambarus]

On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> For NOR flashes EC and VID are zeroed out before an erase is issued to
> make sure UBI does not mistakenly treat the PEB as used and associate it
> with an LEB.
> 
> But on some flashes, like the Cypress Semper S28 SPI NOR flash family,
> multi-pass page programming is not allowed on the default ECC scheme.
> This means zeroing out these magic numbers will result in the flash
> throwing a page programming error.
> 
> Do not zero out EC and VID for such flashes. A writesize > 1 is an
> indication of an ECC-ed flash.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> 
> Notes:
>     Changes in v2:
> 
>     - Use mtd->writesize to check if multi-pass programming can be done
>       instead of using MTD_NO_MULTI_PASS_WRITE.
>     - Remove the assertion that a NOR flash most have writesize of 1.
> 
>  drivers/mtd/ubi/build.c | 4 +---
>  drivers/mtd/ubi/io.c    | 9 ++++++++-
>  2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
> index e85b04e9716b..25fd7816b1f4 100644
> --- a/drivers/mtd/ubi/build.c
> +++ b/drivers/mtd/ubi/build.c
> @@ -628,10 +628,8 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024)
>                 ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024);
>         }
> 
> -       if (ubi->mtd->type == MTD_NORFLASH) {
> -               ubi_assert(ubi->mtd->writesize == 1);
> +       if (ubi->mtd->type == MTD_NORFLASH)
>                 ubi->nor_flash = 1;
> -       }
> 
>         ubi->min_io_size = ubi->mtd->writesize;
>         ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft;
> diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
> index 14d890b00d2c..2f3312c31e51 100644
> --- a/drivers/mtd/ubi/io.c
> +++ b/drivers/mtd/ubi/io.c
> @@ -535,7 +535,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture)
>                 return -EROFS;
>         }
> 
> -       if (ubi->nor_flash) {
> +       /*
> +        * If the flash is ECC-ed then we have to erase the ECC block before we
> +        * can write to it. But the write is in preparation to an erase in the
> +        * first place. This means we cannot zero out EC and VID before the
> +        * erase and we just have to hope the flash starts erasing from the
> +        * start of the page.
> +        */
> +       if (ubi->nor_flash && ubi->mtd->writesize == 1) {

Are there any SPI NORs with ECC block size of 4 bytes? Should we call
nor_erase_prepare() in this case?

Anyway, there's none in SPI NOR as of now, so:

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

>                 err = nor_erase_prepare(ubi, pnum);
>                 if (err)
>                         return err;
> --
> 2.28.0
> 

Re: [PATCH v2 2/3] mtd: spi-nor: core: Allow flashes to specify MTD writesize

[Tudor.Ambarus]

On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
> multi-pass writes to an ECC block is not allowed. In other words, once
> data is programmed to an ECC block, it can't be programmed again without
> erasing it first.
> 
> Upper layers like file systems need to be given this information so they
> do not cause error conditions on the flash by attempting multi-pass
> programming. This can be done by setting 'writesize' in 'struct
> mtd_info'.
> 
> Set the default to 1 but allow flashes to modify it in fixup hooks. If
> more flashes show up with this constraint in the future it might be
> worth it to add it to 'struct flash_info', but for now increasing its
> size is not worth it.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> 
> Notes:
>     New in v2.
> 
>  drivers/mtd/spi-nor/core.c | 4 +++-
>  drivers/mtd/spi-nor/core.h | 3 +++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 5bee7c8da4dc..80fbcb9c0828 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -3054,6 +3054,8 @@ static int spi_nor_init_params(struct spi_nor *nor)
>         if (!nor->params)
>                 return -ENOMEM;
> 
> +       nor->params->writesize = 1;
> +

please do default inits in spi_nor_info_init_params(). A good place would be:

--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2885,6 +2885,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
        nor->flags |= SNOR_F_HAS_16BIT_SR;
 
        /* Set SPI NOR sizes. */
+       params->writesize = 1;
        params->size = (u64)info->sector_size * info->n_sectors;
        params->page_size = info->page_size;


>         spi_nor_info_init_params(nor);
> 
>         spi_nor_manufacturer_init_params(nor);
> @@ -3430,7 +3432,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
>                 mtd->name = dev_name(dev);
>         mtd->priv = nor;
>         mtd->type = MTD_NORFLASH;
> -       mtd->writesize = 1;
> +       mtd->writesize = nor->params->writesize;
>         mtd->flags = MTD_CAP_NORFLASH;
>         mtd->size = nor->params->size;
>         mtd->_erase = spi_nor_erase;
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 0a775a7b5606..413ea311e632 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -197,6 +197,8 @@ struct spi_nor_locking_ops {
>   * @rdsr_dummy:                dummy cycles needed for Read Status Register command.
>   * @rdsr_addr_nbytes:  dummy address bytes needed for Read Status Register
>   *                     command.
> + * @writesize          Minimal writable flash unit size. Defaults to 1. Set to
> + *                     ECC unit size for ECC-ed flashes.
>   * @hwcaps:            describes the read and page program hardware
>   *                     capabilities.
>   * @reads:             read capabilities ordered by priority: the higher index
> @@ -222,6 +224,7 @@ struct spi_nor_flash_parameter {
>         u32                             page_size;

I would put writesize before or after page_size, because they are related.
Also, it would probably avoid padding.

With these addressed, one can add:

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

>         u8                              rdsr_dummy;
>         u8                              rdsr_addr_nbytes;
> +       u32                             writesize;
> 
>         struct spi_nor_hwcaps           hwcaps;
>         struct spi_nor_read_command     reads[SNOR_CMD_READ_MAX];
> --
> 2.28.0
> 

Re: [PATCH v2 3/3] mtd: spi-nor: spansion: Set ECC block size

[Tudor.Ambarus]

On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The S28 flash family uses 2-bit ECC by default with each ECC block being
> 16 bytes. Under this scheme multi-pass programming to an ECC block is
> not allowed. Set the writesize to make sure multi-pass programming is
> not attempted on the flash.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

> ---
> 
> Notes:
>     New in v2.
> 
>  drivers/mtd/spi-nor/spansion.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index e487fd341a56..b0c5521c1e27 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -109,6 +109,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
>  static void s28hs512t_default_init(struct spi_nor *nor)
>  {
>         nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
> +       nor->params->writesize = 16;
>  }
> 
>  static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
> --
> 2.28.0
> 

Re: [PATCH v2 2/3] mtd: spi-nor: core: Allow flashes to specify MTD writesize

[Pratyush Yadav]

On 28/11/20 10:59AM, Tudor.Ambarus@microchip.com wrote:
> On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
> > multi-pass writes to an ECC block is not allowed. In other words, once
> > data is programmed to an ECC block, it can't be programmed again without
> > erasing it first.
> > 
> > Upper layers like file systems need to be given this information so they
> > do not cause error conditions on the flash by attempting multi-pass
> > programming. This can be done by setting 'writesize' in 'struct
> > mtd_info'.
> > 
> > Set the default to 1 but allow flashes to modify it in fixup hooks. If
> > more flashes show up with this constraint in the future it might be
> > worth it to add it to 'struct flash_info', but for now increasing its
> > size is not worth it.
> > 
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > 
> > Notes:
> >     New in v2.
> > 
> >  drivers/mtd/spi-nor/core.c | 4 +++-
> >  drivers/mtd/spi-nor/core.h | 3 +++
> >  2 files changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> > index 5bee7c8da4dc..80fbcb9c0828 100644
> > --- a/drivers/mtd/spi-nor/core.c
> > +++ b/drivers/mtd/spi-nor/core.c
> > @@ -3054,6 +3054,8 @@ static int spi_nor_init_params(struct spi_nor *nor)
> >         if (!nor->params)
> >                 return -ENOMEM;
> > 
> > +       nor->params->writesize = 1;
> > +
> 
> please do default inits in spi_nor_info_init_params(). A good place would be:
> 
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2885,6 +2885,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
>         nor->flags |= SNOR_F_HAS_16BIT_SR;
>  
>         /* Set SPI NOR sizes. */
> +       params->writesize = 1;
>         params->size = (u64)info->sector_size * info->n_sectors;
>         params->page_size = info->page_size;

Ok.
 
> 
> >         spi_nor_info_init_params(nor);
> > 
> >         spi_nor_manufacturer_init_params(nor);
> > @@ -3430,7 +3432,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
> >                 mtd->name = dev_name(dev);
> >         mtd->priv = nor;
> >         mtd->type = MTD_NORFLASH;
> > -       mtd->writesize = 1;
> > +       mtd->writesize = nor->params->writesize;
> >         mtd->flags = MTD_CAP_NORFLASH;
> >         mtd->size = nor->params->size;
> >         mtd->_erase = spi_nor_erase;
> > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> > index 0a775a7b5606..413ea311e632 100644
> > --- a/drivers/mtd/spi-nor/core.h
> > +++ b/drivers/mtd/spi-nor/core.h
> > @@ -197,6 +197,8 @@ struct spi_nor_locking_ops {
> >   * @rdsr_dummy:                dummy cycles needed for Read Status Register command.
> >   * @rdsr_addr_nbytes:  dummy address bytes needed for Read Status Register
> >   *                     command.
> > + * @writesize          Minimal writable flash unit size. Defaults to 1. Set to
> > + *                     ECC unit size for ECC-ed flashes.
> >   * @hwcaps:            describes the read and page program hardware
> >   *                     capabilities.
> >   * @reads:             read capabilities ordered by priority: the higher index
> > @@ -222,6 +224,7 @@ struct spi_nor_flash_parameter {
> >         u32                             page_size;
> 
> I would put writesize before or after page_size, because they are related.
> Also, it would probably avoid padding.

Ok.
 
> With these addressed, one can add:
> 
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Thanks.
 
> >         u8                              rdsr_dummy;
> >         u8                              rdsr_addr_nbytes;
> > +       u32                             writesize;
> > 
> >         struct spi_nor_hwcaps           hwcaps;
> >         struct spi_nor_read_command     reads[SNOR_CMD_READ_MAX];
> > --
> > 2.28.0
> > 
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments India

Re: [PATCH v2 1/3] UBI: Do not zero out EC and VID on ECC-ed NOR flashes

[Pratyush Yadav]

On 28/11/20 10:58AM, Tudor.Ambarus@microchip.com wrote:
> On 11/18/20 8:24 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > For NOR flashes EC and VID are zeroed out before an erase is issued to
> > make sure UBI does not mistakenly treat the PEB as used and associate it
> > with an LEB.
> > 
> > But on some flashes, like the Cypress Semper S28 SPI NOR flash family,
> > multi-pass page programming is not allowed on the default ECC scheme.
> > This means zeroing out these magic numbers will result in the flash
> > throwing a page programming error.
> > 
> > Do not zero out EC and VID for such flashes. A writesize > 1 is an
> > indication of an ECC-ed flash.
> > 
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > 
> > Notes:
> >     Changes in v2:
> > 
> >     - Use mtd->writesize to check if multi-pass programming can be done
> >       instead of using MTD_NO_MULTI_PASS_WRITE.
> >     - Remove the assertion that a NOR flash most have writesize of 1.
> > 
> >  drivers/mtd/ubi/build.c | 4 +---
> >  drivers/mtd/ubi/io.c    | 9 ++++++++-
> >  2 files changed, 9 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
> > index e85b04e9716b..25fd7816b1f4 100644
> > --- a/drivers/mtd/ubi/build.c
> > +++ b/drivers/mtd/ubi/build.c
> > @@ -628,10 +628,8 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024)
> >                 ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024);
> >         }
> > 
> > -       if (ubi->mtd->type == MTD_NORFLASH) {
> > -               ubi_assert(ubi->mtd->writesize == 1);
> > +       if (ubi->mtd->type == MTD_NORFLASH)
> >                 ubi->nor_flash = 1;
> > -       }
> > 
> >         ubi->min_io_size = ubi->mtd->writesize;
> >         ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft;
> > diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
> > index 14d890b00d2c..2f3312c31e51 100644
> > --- a/drivers/mtd/ubi/io.c
> > +++ b/drivers/mtd/ubi/io.c
> > @@ -535,7 +535,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture)
> >                 return -EROFS;
> >         }
> > 
> > -       if (ubi->nor_flash) {
> > +       /*
> > +        * If the flash is ECC-ed then we have to erase the ECC block before we
> > +        * can write to it. But the write is in preparation to an erase in the
> > +        * first place. This means we cannot zero out EC and VID before the
> > +        * erase and we just have to hope the flash starts erasing from the
> > +        * start of the page.
> > +        */
> > +       if (ubi->nor_flash && ubi->mtd->writesize == 1) {
> 
> Are there any SPI NORs with ECC block size of 4 bytes? Should we call
> nor_erase_prepare() in this case?

None that I know of. But even if there was such a flash this check would 
continue to be correct.

Like Vignesh explained in the previous version, mtd->writesize > 1 means 
that multi-pass writes are not allowed in that ECC block. So even if a 
flash has ECC block size of 4, we still are not allowed to write 4 (or 
less) bytes to it before erasing first.
 
> Anyway, there's none in SPI NOR as of now, so:
> 
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> 
> >                 err = nor_erase_prepare(ubi, pnum);
> >                 if (err)
> >                         return err;
> > --
> > 2.28.0
> > 
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments India