linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v4 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
@ 2020-12-07  9:00 Troy Lee
  2020-12-07  9:00 ` [PATCH v4 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree Troy Lee
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Troy Lee @ 2020-12-07  9:00 UTC (permalink / raw)
  To: Stefan Schaeckeler, Rob Herring, Joel Stanley, Andrew Jeffery,
	Borislav Petkov, Mauro Carvalho Chehab, Tony Luck, James Morse,
	Robert Richter,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	open list:EDAC-CORE
  Cc: leetroy, troy_lee, ryan_chen

Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Acked-by: Joel Stanley <joel@jms.id.au>
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt       | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+	- "aspeed,ast2400-sdram-edac"
+	- "aspeed,ast2500-sdram-edac"
+	- "aspeed,ast2600-sdram-edac"
 - reg:        sdram controller register set should be <0x1e6e0000 0x174>
 - interrupts: should be AVIC interrupt #0
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-12-07 11:55 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-07  9:00 [PATCH v4 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support Troy Lee
2020-12-07  9:00 ` [PATCH v4 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree Troy Lee
2020-12-07  9:00 ` [PATCH v4 3/3] edac: Supporting AST2400 and AST2600 edac driver Troy Lee
2020-12-07  9:10   ` Stefan Schaeckeler (sschaeck)
2020-12-07 11:53   ` Joel Stanley
2020-12-07 11:11 ` [PATCH v4 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support Borislav Petkov

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).