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From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	devel@driverdev.osuosl.org, linux-sunxi@googlegroups.com
Cc: "Yong Deng" <yong.deng@magewell.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@siol.net>,
	"Paul Kocialkowski" <paul.kocialkowski@bootlin.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Helen Koike" <helen.koike@collabora.com>,
	"Dafna Hirschfeld" <dafna.hirschfeld@collabora.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Sakari Ailus" <sakari.ailus@linux.intel.com>,
	"Hans Verkuil" <hans.verkuil@cisco.com>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	kevin.lhopital@hotmail.com,
	"Kévin L'hôpital" <kevin.lhopital@bootlin.com>
Subject: [PATCH v3 05/15] media: sun6i-csi: Only configure the interface data width for parallel
Date: Fri, 11 Dec 2020 16:56:58 +0100	[thread overview]
Message-ID: <20201211155708.154710-6-paul.kocialkowski@bootlin.com> (raw)
In-Reply-To: <20201211155708.154710-1-paul.kocialkowski@bootlin.com>

Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.

In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.

Co-developed-by: Kévin L'hôpital <kevin.lhopital@bootlin.com>
Signed-off-by: Kévin L'hôpital <kevin.lhopital@bootlin.com>
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
 .../platform/sunxi/sun6i-csi/sun6i_csi.c      | 42 +++++++++++--------
 1 file changed, 25 insertions(+), 17 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 531a4cccd14a..f1150de94e98 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
 	unsigned char bus_width;
 	u32 flags;
 	u32 cfg;
+	bool input_parallel = false;
 	bool input_interlaced = false;
 
+	if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+	    endpoint->bus_type == V4L2_MBUS_BT656)
+		input_parallel = true;
+
 	if (csi->config.field == V4L2_FIELD_INTERLACED
 	    || csi->config.field == V4L2_FIELD_INTERLACED_TB
 	    || csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
 		 CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
 		 CSI_IF_CFG_SRC_TYPE_MASK);
 
+	if (input_parallel) {
+		switch (bus_width) {
+		case 8:
+			cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+			break;
+		case 10:
+			cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+			break;
+		case 12:
+			cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+			break;
+		case 16: /* No need to configure DATA_WIDTH for 16bit */
+			break;
+		default:
+			dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+				 bus_width);
+			break;
+		}
+	}
+
 	if (input_interlaced)
 		cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
 	else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
 		break;
 	}
 
-	switch (bus_width) {
-	case 8:
-		cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
-		break;
-	case 10:
-		cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
-		break;
-	case 12:
-		cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
-		break;
-	case 16: /* No need to configure DATA_WIDTH for 16bit */
-		break;
-	default:
-		dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
-		break;
-	}
-
 	regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
 }
 
-- 
2.29.2


  parent reply	other threads:[~2020-12-11 16:59 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-11 15:56 [PATCH v3 00/15] Allwinner MIPI CSI-2 support for A31/V3s/A83T Paul Kocialkowski
2020-12-11 15:56 ` [PATCH v3 01/15] docs: phy: Add a part about PHY mode and submode Paul Kocialkowski
2020-12-11 15:56 ` [PATCH v3 02/15] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Paul Kocialkowski
2020-12-11 15:56 ` [PATCH v3 03/15] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2 Paul Kocialkowski
2020-12-11 15:56 ` [PATCH v3 04/15] media: sun6i-csi: Use common V4L2 format info for storage bpp Paul Kocialkowski
2020-12-11 15:56 ` Paul Kocialkowski [this message]
2020-12-11 15:56 ` [PATCH v3 06/15] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port Paul Kocialkowski
2020-12-14 23:12   ` Rob Herring
2020-12-11 15:57 ` [PATCH v3 07/15] media: sun6i-csi: Add support for MIPI CSI-2 bridge input Paul Kocialkowski
2020-12-14 11:34   ` Maxime Ripard
2020-12-11 15:57 ` [PATCH v3 08/15] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation Paul Kocialkowski
2020-12-14 11:35   ` Maxime Ripard
2020-12-14 23:14     ` Rob Herring
2020-12-11 15:57 ` [PATCH v3 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller Paul Kocialkowski
2020-12-14 11:39   ` Maxime Ripard
2020-12-31 12:54     ` Paul Kocialkowski
2020-12-11 15:57 ` [PATCH v3 10/15] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Paul Kocialkowski
2020-12-11 15:57 ` [PATCH v3 11/15] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge Paul Kocialkowski
2020-12-11 15:57 ` [PATCH v3 12/15] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation Paul Kocialkowski
2020-12-11 15:57 ` [PATCH v3 13/15] media: sunxi: Add support for the A83T MIPI CSI-2 controller Paul Kocialkowski
2020-12-14 11:41   ` Maxime Ripard
2020-12-11 15:57 ` [PATCH v3 14/15] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node Paul Kocialkowski
2020-12-11 15:57 ` [PATCH v3 15/15] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge Paul Kocialkowski

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