* drivers/clk/imx/clk-imx8mp.c:446:25: sparse: sparse: incorrect type in argument 1 (different address spaces)
@ 2020-12-14 17:19 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2020-12-14 17:19 UTC (permalink / raw)
To: Anson Huang
Cc: kbuild-all, linux-kernel, Shawn Guo, Dong Aisheng, Stephen Boyd
[-- Attachment #1: Type: text/plain, Size: 45958 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2c85ebc57b3e1817b6ce1a6b703928e113a90442
commit: 9a976cd278eafa496ce30196810ef2e879a4a7d5 clk: imx8m: Support module build
date: 4 months ago
config: openrisc-randconfig-s031-20201214 (attached as .config)
compiler: or1k-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-184-g1b896707-dirty
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9a976cd278eafa496ce30196810ef2e879a4a7d5
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 9a976cd278eafa496ce30196810ef2e879a4a7d5
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=openrisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/clk/imx/clk-imx8mp.c:446:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void *addr @@ got void [noderef] __iomem *[assigned] anatop_base @@
drivers/clk/imx/clk-imx8mp.c:446:25: sparse: expected void *addr
drivers/clk/imx/clk-imx8mp.c:446:25: sparse: got void [noderef] __iomem *[assigned] anatop_base
drivers/clk/imx/clk-imx8mp.c:452:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void *addr @@ got void [noderef] __iomem *[assigned] anatop_base @@
drivers/clk/imx/clk-imx8mp.c:452:25: sparse: expected void *addr
drivers/clk/imx/clk-imx8mp.c:452:25: sparse: got void [noderef] __iomem *[assigned] anatop_base
vim +446 drivers/clk/imx/clk-imx8mp.c
9c140d9926761b0 Anson Huang 2020-01-08 429
9c140d9926761b0 Anson Huang 2020-01-08 430 static int imx8mp_clocks_probe(struct platform_device *pdev)
9c140d9926761b0 Anson Huang 2020-01-08 431 {
9c140d9926761b0 Anson Huang 2020-01-08 432 struct device *dev = &pdev->dev;
9c140d9926761b0 Anson Huang 2020-01-08 433 struct device_node *np = dev->of_node;
9c140d9926761b0 Anson Huang 2020-01-08 434 void __iomem *anatop_base, *ccm_base;
9c140d9926761b0 Anson Huang 2020-01-08 435 int i;
9c140d9926761b0 Anson Huang 2020-01-08 436
9c140d9926761b0 Anson Huang 2020-01-08 437 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
9c140d9926761b0 Anson Huang 2020-01-08 438 anatop_base = of_iomap(np, 0);
680fbce528169ea Anson Huang 2020-02-12 439 of_node_put(np);
9c140d9926761b0 Anson Huang 2020-01-08 440 if (WARN_ON(!anatop_base))
9c140d9926761b0 Anson Huang 2020-01-08 441 return -ENOMEM;
9c140d9926761b0 Anson Huang 2020-01-08 442
9c140d9926761b0 Anson Huang 2020-01-08 443 np = dev->of_node;
9c140d9926761b0 Anson Huang 2020-01-08 444 ccm_base = devm_platform_ioremap_resource(pdev, 0);
9c140d9926761b0 Anson Huang 2020-01-08 445 if (WARN_ON(IS_ERR(ccm_base))) {
9c140d9926761b0 Anson Huang 2020-01-08 @446 iounmap(anatop_base);
9c140d9926761b0 Anson Huang 2020-01-08 447 return PTR_ERR(ccm_base);
9c140d9926761b0 Anson Huang 2020-01-08 448 }
9c140d9926761b0 Anson Huang 2020-01-08 449
9c140d9926761b0 Anson Huang 2020-01-08 450 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
9c140d9926761b0 Anson Huang 2020-01-08 451 if (WARN_ON(!clk_hw_data)) {
9c140d9926761b0 Anson Huang 2020-01-08 452 iounmap(anatop_base);
9c140d9926761b0 Anson Huang 2020-01-08 453 return -ENOMEM;
9c140d9926761b0 Anson Huang 2020-01-08 454 }
9c140d9926761b0 Anson Huang 2020-01-08 455
9c140d9926761b0 Anson Huang 2020-01-08 456 clk_hw_data->num = IMX8MP_CLK_END;
9c140d9926761b0 Anson Huang 2020-01-08 457 hws = clk_hw_data->hws;
9c140d9926761b0 Anson Huang 2020-01-08 458
9c140d9926761b0 Anson Huang 2020-01-08 459 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
9c140d9926761b0 Anson Huang 2020-01-08 460 hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
9c140d9926761b0 Anson Huang 2020-01-08 461 hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
9c140d9926761b0 Anson Huang 2020-01-08 462 hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
9c140d9926761b0 Anson Huang 2020-01-08 463 hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
9c140d9926761b0 Anson Huang 2020-01-08 464 hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
9c140d9926761b0 Anson Huang 2020-01-08 465 hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
9c140d9926761b0 Anson Huang 2020-01-08 466
9c140d9926761b0 Anson Huang 2020-01-08 467 hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 468 hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 469 hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 470 hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 471 hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 472 hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 473 hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 474 hws[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 475 hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 476 hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
9c140d9926761b0 Anson Huang 2020-01-08 477
9c140d9926761b0 Anson Huang 2020-01-08 478 hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 479 hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 480 hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 481 hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll);
9c140d9926761b0 Anson Huang 2020-01-08 482 hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 483 hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 484 hws[IMX8MP_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 485 hws[IMX8MP_SYS_PLL1] = imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 486 hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 487 hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
9c140d9926761b0 Anson Huang 2020-01-08 488
dc6e21da3402976 Peng Fan 2020-05-07 489 hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 490 hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 491 hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 492 hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 493 hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 494 hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 495 hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 496 hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 497 hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
dc6e21da3402976 Peng Fan 2020-05-07 498 hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
9c140d9926761b0 Anson Huang 2020-01-08 499
9c140d9926761b0 Anson Huang 2020-01-08 500 hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
9c140d9926761b0 Anson Huang 2020-01-08 501 hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
9c140d9926761b0 Anson Huang 2020-01-08 502 hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13);
9c140d9926761b0 Anson Huang 2020-01-08 503 hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13);
9c140d9926761b0 Anson Huang 2020-01-08 504 hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
9c140d9926761b0 Anson Huang 2020-01-08 505 hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
9c140d9926761b0 Anson Huang 2020-01-08 506 hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
9c140d9926761b0 Anson Huang 2020-01-08 507 hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
9c140d9926761b0 Anson Huang 2020-01-08 508
77f5d2d97353149 Peng Fan 2020-05-07 509 hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
77f5d2d97353149 Peng Fan 2020-05-07 510 hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
77f5d2d97353149 Peng Fan 2020-05-07 511 hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
77f5d2d97353149 Peng Fan 2020-05-07 512 hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
77f5d2d97353149 Peng Fan 2020-05-07 513 hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
77f5d2d97353149 Peng Fan 2020-05-07 514 hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
77f5d2d97353149 Peng Fan 2020-05-07 515 hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
77f5d2d97353149 Peng Fan 2020-05-07 516 hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
77f5d2d97353149 Peng Fan 2020-05-07 517 hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
77f5d2d97353149 Peng Fan 2020-05-07 518
77f5d2d97353149 Peng Fan 2020-05-07 519 hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
77f5d2d97353149 Peng Fan 2020-05-07 520 hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
77f5d2d97353149 Peng Fan 2020-05-07 521 hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
77f5d2d97353149 Peng Fan 2020-05-07 522 hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
77f5d2d97353149 Peng Fan 2020-05-07 523 hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
77f5d2d97353149 Peng Fan 2020-05-07 524 hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
77f5d2d97353149 Peng Fan 2020-05-07 525 hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
77f5d2d97353149 Peng Fan 2020-05-07 526 hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
9c140d9926761b0 Anson Huang 2020-01-08 527 hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
9c140d9926761b0 Anson Huang 2020-01-08 528
77f5d2d97353149 Peng Fan 2020-05-07 529 hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
77f5d2d97353149 Peng Fan 2020-05-07 530 hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
77f5d2d97353149 Peng Fan 2020-05-07 531 hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
77f5d2d97353149 Peng Fan 2020-05-07 532 hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
77f5d2d97353149 Peng Fan 2020-05-07 533 hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
77f5d2d97353149 Peng Fan 2020-05-07 534 hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
77f5d2d97353149 Peng Fan 2020-05-07 535 hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
77f5d2d97353149 Peng Fan 2020-05-07 536 hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
77f5d2d97353149 Peng Fan 2020-05-07 537 hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
77f5d2d97353149 Peng Fan 2020-05-07 538
77f5d2d97353149 Peng Fan 2020-05-07 539 hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
77f5d2d97353149 Peng Fan 2020-05-07 540 hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
77f5d2d97353149 Peng Fan 2020-05-07 541 hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
77f5d2d97353149 Peng Fan 2020-05-07 542 hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
77f5d2d97353149 Peng Fan 2020-05-07 543 hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
77f5d2d97353149 Peng Fan 2020-05-07 544 hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
77f5d2d97353149 Peng Fan 2020-05-07 545 hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
77f5d2d97353149 Peng Fan 2020-05-07 546 hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
9c140d9926761b0 Anson Huang 2020-01-08 547 hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
9c140d9926761b0 Anson Huang 2020-01-08 548
8c83a8ff4dd9287 Peng Fan 2020-05-07 549 hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
8c83a8ff4dd9287 Peng Fan 2020-05-07 550 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
8c83a8ff4dd9287 Peng Fan 2020-05-07 551 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
8c83a8ff4dd9287 Peng Fan 2020-05-07 552 hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
8c83a8ff4dd9287 Peng Fan 2020-05-07 553 hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
8c83a8ff4dd9287 Peng Fan 2020-05-07 554 hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
8c83a8ff4dd9287 Peng Fan 2020-05-07 555 hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
8c83a8ff4dd9287 Peng Fan 2020-05-07 556 hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280);
8c83a8ff4dd9287 Peng Fan 2020-05-07 557 hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300);
8c83a8ff4dd9287 Peng Fan 2020-05-07 558 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
8c83a8ff4dd9287 Peng Fan 2020-05-07 559 hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380);
8c83a8ff4dd9287 Peng Fan 2020-05-07 560 hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400);
9c140d9926761b0 Anson Huang 2020-01-08 561
7ab227210110a41 Peng Fan 2020-02-19 562 /* CORE SEL */
0d77abc4fc31e03 Anson Huang 2020-02-25 563 hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
7ab227210110a41 Peng Fan 2020-02-19 564
9c140d9926761b0 Anson Huang 2020-01-08 565 hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
b1657ad708f761f Peng Fan 2020-05-07 566 hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
9c140d9926761b0 Anson Huang 2020-01-08 567 hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
b1657ad708f761f Peng Fan 2020-05-07 568 hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
b1657ad708f761f Peng Fan 2020-05-07 569 hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
b1657ad708f761f Peng Fan 2020-05-07 570 hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
b1657ad708f761f Peng Fan 2020-05-07 571 hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
b1657ad708f761f Peng Fan 2020-05-07 572 hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
b1657ad708f761f Peng Fan 2020-05-07 573 hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
b1657ad708f761f Peng Fan 2020-05-07 574 hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
9c140d9926761b0 Anson Huang 2020-01-08 575 hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
9c140d9926761b0 Anson Huang 2020-01-08 576 hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
b1657ad708f761f Peng Fan 2020-05-07 577 hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
b1657ad708f761f Peng Fan 2020-05-07 578 hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
9c140d9926761b0 Anson Huang 2020-01-08 579
9c140d9926761b0 Anson Huang 2020-01-08 580 hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
b1657ad708f761f Peng Fan 2020-05-07 581 hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
b1657ad708f761f Peng Fan 2020-05-07 582 hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
9c140d9926761b0 Anson Huang 2020-01-08 583
9c140d9926761b0 Anson Huang 2020-01-08 584 hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
9c140d9926761b0 Anson Huang 2020-01-08 585 hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
9c140d9926761b0 Anson Huang 2020-01-08 586
9c140d9926761b0 Anson Huang 2020-01-08 587 hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
9c140d9926761b0 Anson Huang 2020-01-08 588 hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
9c140d9926761b0 Anson Huang 2020-01-08 589 hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
9c140d9926761b0 Anson Huang 2020-01-08 590 hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
9c140d9926761b0 Anson Huang 2020-01-08 591 hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
9c140d9926761b0 Anson Huang 2020-01-08 592 hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
9c140d9926761b0 Anson Huang 2020-01-08 593 hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300);
9c140d9926761b0 Anson Huang 2020-01-08 594 hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
9c140d9926761b0 Anson Huang 2020-01-08 595 hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
9c140d9926761b0 Anson Huang 2020-01-08 596 hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
9c140d9926761b0 Anson Huang 2020-01-08 597 hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500);
9c140d9926761b0 Anson Huang 2020-01-08 598 hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
9c140d9926761b0 Anson Huang 2020-01-08 599 hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
9c140d9926761b0 Anson Huang 2020-01-08 600 hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
9c140d9926761b0 Anson Huang 2020-01-08 601 hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700);
9c140d9926761b0 Anson Huang 2020-01-08 602 hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
9c140d9926761b0 Anson Huang 2020-01-08 603 hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
9c140d9926761b0 Anson Huang 2020-01-08 604 hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);
9c140d9926761b0 Anson Huang 2020-01-08 605 hws[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900);
9c140d9926761b0 Anson Huang 2020-01-08 606 hws[IMX8MP_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, ccm_base + 0xa980);
9c140d9926761b0 Anson Huang 2020-01-08 607 hws[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, ccm_base + 0xaa00);
9c140d9926761b0 Anson Huang 2020-01-08 608 hws[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm_base + 0xaa80);
9c140d9926761b0 Anson Huang 2020-01-08 609 hws[IMX8MP_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, ccm_base + 0xab00);
9c140d9926761b0 Anson Huang 2020-01-08 610 hws[IMX8MP_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, ccm_base + 0xab80);
9c140d9926761b0 Anson Huang 2020-01-08 611 hws[IMX8MP_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, ccm_base + 0xac00);
9c140d9926761b0 Anson Huang 2020-01-08 612 hws[IMX8MP_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, ccm_base + 0xac80);
9c140d9926761b0 Anson Huang 2020-01-08 613 hws[IMX8MP_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, ccm_base + 0xad00);
9c140d9926761b0 Anson Huang 2020-01-08 614 hws[IMX8MP_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, ccm_base + 0xad80);
9c140d9926761b0 Anson Huang 2020-01-08 615 hws[IMX8MP_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, ccm_base + 0xae00);
9c140d9926761b0 Anson Huang 2020-01-08 616 hws[IMX8MP_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, ccm_base + 0xae80);
9c140d9926761b0 Anson Huang 2020-01-08 617
9c140d9926761b0 Anson Huang 2020-01-08 618 hws[IMX8MP_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, ccm_base + 0xaf00);
9c140d9926761b0 Anson Huang 2020-01-08 619 hws[IMX8MP_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, ccm_base + 0xaf80);
9c140d9926761b0 Anson Huang 2020-01-08 620 hws[IMX8MP_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, ccm_base + 0xb000);
9c140d9926761b0 Anson Huang 2020-01-08 621 hws[IMX8MP_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, ccm_base + 0xb080);
9c140d9926761b0 Anson Huang 2020-01-08 622 hws[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm_base + 0xb100);
9c140d9926761b0 Anson Huang 2020-01-08 623 hws[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm_base + 0xb180);
9c140d9926761b0 Anson Huang 2020-01-08 624 hws[IMX8MP_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, ccm_base + 0xb200);
9c140d9926761b0 Anson Huang 2020-01-08 625 hws[IMX8MP_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, ccm_base + 0xb280);
9c140d9926761b0 Anson Huang 2020-01-08 626 hws[IMX8MP_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, ccm_base + 0xb300);
9c140d9926761b0 Anson Huang 2020-01-08 627 hws[IMX8MP_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, ccm_base + 0xb380);
9c140d9926761b0 Anson Huang 2020-01-08 628 hws[IMX8MP_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, ccm_base + 0xb400);
9c140d9926761b0 Anson Huang 2020-01-08 629 hws[IMX8MP_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, ccm_base + 0xb480);
9c140d9926761b0 Anson Huang 2020-01-08 630 hws[IMX8MP_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, ccm_base + 0xb500);
9c140d9926761b0 Anson Huang 2020-01-08 631
9c140d9926761b0 Anson Huang 2020-01-08 632 hws[IMX8MP_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, ccm_base + 0xb580);
9c140d9926761b0 Anson Huang 2020-01-08 633 hws[IMX8MP_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, ccm_base + 0xb600);
9c140d9926761b0 Anson Huang 2020-01-08 634 hws[IMX8MP_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, ccm_base + 0xb680);
9c140d9926761b0 Anson Huang 2020-01-08 635 hws[IMX8MP_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, ccm_base + 0xb700);
9c140d9926761b0 Anson Huang 2020-01-08 636 hws[IMX8MP_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, ccm_base + 0xb780);
9c140d9926761b0 Anson Huang 2020-01-08 637 hws[IMX8MP_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, ccm_base + 0xb800);
9c140d9926761b0 Anson Huang 2020-01-08 638 hws[IMX8MP_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, ccm_base + 0xb900);
9c140d9926761b0 Anson Huang 2020-01-08 639 hws[IMX8MP_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, ccm_base + 0xb980);
9c140d9926761b0 Anson Huang 2020-01-08 640 hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00);
9c140d9926761b0 Anson Huang 2020-01-08 641 hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80);
9c140d9926761b0 Anson Huang 2020-01-08 642 hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00);
c267bd443f38972 Anson Huang 2020-02-19 643 hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80);
9c140d9926761b0 Anson Huang 2020-01-08 644 hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00);
9c140d9926761b0 Anson Huang 2020-01-08 645 hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
9c140d9926761b0 Anson Huang 2020-01-08 646 hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
9c140d9926761b0 Anson Huang 2020-01-08 647 hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
9c140d9926761b0 Anson Huang 2020-01-08 648 hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
9c140d9926761b0 Anson Huang 2020-01-08 649 hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
9c140d9926761b0 Anson Huang 2020-01-08 650 hws[IMX8MP_CLK_MEDIA_MIPI_PHY2_REF] = imx8m_clk_hw_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm_base + 0xbf00);
9c140d9926761b0 Anson Huang 2020-01-08 651 hws[IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC] = imx8m_clk_hw_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm_base + 0xbf80);
9c140d9926761b0 Anson Huang 2020-01-08 652 hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
9c140d9926761b0 Anson Huang 2020-01-08 653 hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
9c140d9926761b0 Anson Huang 2020-01-08 654 hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
9c140d9926761b0 Anson Huang 2020-01-08 655 hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);
9c140d9926761b0 Anson Huang 2020-01-08 656 hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200);
9c140d9926761b0 Anson Huang 2020-01-08 657 hws[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm_base + 0xc280);
9c140d9926761b0 Anson Huang 2020-01-08 658 hws[IMX8MP_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, ccm_base + 0xc300);
9c140d9926761b0 Anson Huang 2020-01-08 659
9c140d9926761b0 Anson Huang 2020-01-08 660 hws[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
9c140d9926761b0 Anson Huang 2020-01-08 661 hws[IMX8MP_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", ccm_base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL);
9c140d9926761b0 Anson Huang 2020-01-08 662
9c140d9926761b0 Anson Huang 2020-01-08 663 hws[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL);
9c140d9926761b0 Anson Huang 2020-01-08 664 hws[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", ccm_base + 0x4070, 0);
9c140d9926761b0 Anson Huang 2020-01-08 665 hws[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", ccm_base + 0x4080, 0);
9c140d9926761b0 Anson Huang 2020-01-08 666 hws[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", ccm_base + 0x4090, 0);
9c140d9926761b0 Anson Huang 2020-01-08 667 hws[IMX8MP_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", ccm_base + 0x40a0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 668 hws[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", ccm_base + 0x40b0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 669 hws[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", ccm_base + 0x40c0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 670 hws[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", ccm_base + 0x40d0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 671 hws[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", ccm_base + 0x40e0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 672 hws[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", ccm_base + 0x40f0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 673 hws[IMX8MP_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", ccm_base + 0x4100, 0);
9c140d9926761b0 Anson Huang 2020-01-08 674 hws[IMX8MP_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", ccm_base + 0x4110, 0);
9c140d9926761b0 Anson Huang 2020-01-08 675 hws[IMX8MP_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", ccm_base + 0x4120, 0);
9c140d9926761b0 Anson Huang 2020-01-08 676 hws[IMX8MP_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", ccm_base + 0x4130, 0);
9c140d9926761b0 Anson Huang 2020-01-08 677 hws[IMX8MP_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", ccm_base + 0x4140, 0);
9c140d9926761b0 Anson Huang 2020-01-08 678 hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0);
9c140d9926761b0 Anson Huang 2020-01-08 679 hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0);
9c140d9926761b0 Anson Huang 2020-01-08 680 hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
9c140d9926761b0 Anson Huang 2020-01-08 681 hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
9c140d9926761b0 Anson Huang 2020-01-08 682 hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
94ae59ac5d12cc9 Peng Fan 2020-06-01 683 hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
14875e57d8ea965 Peng Fan 2020-01-19 684 hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
9c140d9926761b0 Anson Huang 2020-01-08 685 hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
9c140d9926761b0 Anson Huang 2020-01-08 686 hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
9c140d9926761b0 Anson Huang 2020-01-08 687 hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0);
9c140d9926761b0 Anson Huang 2020-01-08 688 hws[IMX8MP_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", ccm_base + 0x42a0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 689 hws[IMX8MP_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", ccm_base + 0x42b0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 690 hws[IMX8MP_CLK_QOS_ROOT] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", ccm_base + 0x42c0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 691 hws[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", ccm_base + 0x42e0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 692 hws[IMX8MP_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", ccm_base + 0x42f0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 693 hws[IMX8MP_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", ccm_base + 0x4300, 0, &share_count_nand);
9c140d9926761b0 Anson Huang 2020-01-08 694 hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_count_nand);
9c140d9926761b0 Anson Huang 2020-01-08 695 hws[IMX8MP_CLK_I2C5_ROOT] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", ccm_base + 0x4330, 0);
9c140d9926761b0 Anson Huang 2020-01-08 696 hws[IMX8MP_CLK_I2C6_ROOT] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", ccm_base + 0x4340, 0);
9c140d9926761b0 Anson Huang 2020-01-08 697 hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
9c140d9926761b0 Anson Huang 2020-01-08 698 hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
9c140d9926761b0 Anson Huang 2020-01-08 699 hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
857c9d31f59f0c0 Fugang Duan 2020-02-19 700 hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 701 hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
8c83a8ff4dd9287 Peng Fan 2020-05-07 702 hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
8c83a8ff4dd9287 Peng Fan 2020-05-07 703 hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
9c140d9926761b0 Anson Huang 2020-01-08 704 hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
9c140d9926761b0 Anson Huang 2020-01-08 705 hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
9c140d9926761b0 Anson Huang 2020-01-08 706 hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 707 hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 708 hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 709 hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 710 hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 711 hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
9c140d9926761b0 Anson Huang 2020-01-08 712 hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
9c140d9926761b0 Anson Huang 2020-01-08 713 hws[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", ccm_base + 0x4530, 0);
9c140d9926761b0 Anson Huang 2020-01-08 714 hws[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", ccm_base + 0x4540, 0);
9c140d9926761b0 Anson Huang 2020-01-08 715 hws[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", ccm_base + 0x4550, 0);
9c140d9926761b0 Anson Huang 2020-01-08 716 hws[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", ccm_base + 0x4560, 0);
9c140d9926761b0 Anson Huang 2020-01-08 717 hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0);
9c140d9926761b0 Anson Huang 2020-01-08 718 hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0);
9c140d9926761b0 Anson Huang 2020-01-08 719 hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
8c83a8ff4dd9287 Peng Fan 2020-05-07 720 hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 721 hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 722 hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 723 hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 724 hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 725 hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 726 hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 727 hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
8c83a8ff4dd9287 Peng Fan 2020-05-07 728 hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
9c140d9926761b0 Anson Huang 2020-01-08 729
9c140d9926761b0 Anson Huang 2020-01-08 730 hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 731 hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
9c140d9926761b0 Anson Huang 2020-01-08 732 hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
9c140d9926761b0 Anson Huang 2020-01-08 733 hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
9c140d9926761b0 Anson Huang 2020-01-08 734 hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
9c140d9926761b0 Anson Huang 2020-01-08 735
7ab227210110a41 Peng Fan 2020-02-19 736 hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
7ab227210110a41 Peng Fan 2020-02-19 737 hws[IMX8MP_CLK_A53_CORE]->clk,
7ab227210110a41 Peng Fan 2020-02-19 738 hws[IMX8MP_CLK_A53_CORE]->clk,
9c140d9926761b0 Anson Huang 2020-01-08 739 hws[IMX8MP_ARM_PLL_OUT]->clk,
7ab227210110a41 Peng Fan 2020-02-19 740 hws[IMX8MP_CLK_A53_DIV]->clk);
9c140d9926761b0 Anson Huang 2020-01-08 741
9c140d9926761b0 Anson Huang 2020-01-08 742 imx_check_clk_hws(hws, IMX8MP_CLK_END);
9c140d9926761b0 Anson Huang 2020-01-08 743
9c140d9926761b0 Anson Huang 2020-01-08 744 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
9c140d9926761b0 Anson Huang 2020-01-08 745
9c140d9926761b0 Anson Huang 2020-01-08 746 for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
9c140d9926761b0 Anson Huang 2020-01-08 747 int index = uart_clk_ids[i];
9c140d9926761b0 Anson Huang 2020-01-08 748
9c140d9926761b0 Anson Huang 2020-01-08 749 uart_clks[i] = &hws[index]->clk;
9c140d9926761b0 Anson Huang 2020-01-08 750 }
9c140d9926761b0 Anson Huang 2020-01-08 751
9c140d9926761b0 Anson Huang 2020-01-08 752 imx_register_uart_clocks(uart_clks);
9c140d9926761b0 Anson Huang 2020-01-08 753
9c140d9926761b0 Anson Huang 2020-01-08 754 return 0;
9c140d9926761b0 Anson Huang 2020-01-08 755 }
9c140d9926761b0 Anson Huang 2020-01-08 756
:::::: The code at line 446 was first introduced by commit
:::::: 9c140d9926761b0f5d329ff6c09a1540f3d5e1d3 clk: imx: Add support for i.MX8MP clock driver
:::::: TO: Anson Huang <Anson.Huang@nxp.com>
:::::: CC: Shawn Guo <shawnguo@kernel.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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