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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Nishanth Menon <nm@ti.com>,
	Philipp Zabel <p.zabel@pengutronix.de>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES
Date: Thu, 24 Dec 2020 16:46:24 +0530	[thread overview]
Message-ID: <20201224111627.32590-13-kishon@ti.com> (raw)
In-Reply-To: <20201224111627.32590-1-kishon@ti.com>

Add DT nodes for clocks within Sierra SERDES.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++--
 1 file changed, 120 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 2d526ea44a85..9d1edce31829 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -400,8 +400,36 @@
 			#size-cells = <0>;
 			resets = <&serdes_wiz0 0>;
 			reset-names = "sierra_reset";
-			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>;
+			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+			serdes0_refrcv: refrcv {
+				clocks = <&wiz0_pll0_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes0_refrcv1: refrcv1 {
+				clocks = <&wiz0_pll1_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes0_pll_cmnlc: pll_cmnlc {
+				clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes0_pll_cmnlc>;
+				assigned-clock-parents = <&wiz0_pll0_refclk>;
+			};
+
+			serdes0_pll_cmnlc1: pll_cmnlc1 {
+				clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes0_pll_cmnlc1>;
+				assigned-clock-parents = <&wiz0_pll1_refclk>;
+			};
 		};
 	};
 
@@ -457,8 +485,36 @@
 			#size-cells = <0>;
 			resets = <&serdes_wiz1 0>;
 			reset-names = "sierra_reset";
-			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>;
+			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+			serdes1_refrcv: refrcv {
+				clocks = <&wiz1_pll0_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes1_refrcv1: refrcv1 {
+				clocks = <&wiz1_pll1_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes1_pll_cmnlc: pll_cmnlc {
+				clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes1_pll_cmnlc>;
+				assigned-clock-parents = <&wiz1_pll0_refclk>;
+			};
+
+			serdes1_pll_cmnlc1: pll_cmnlc1 {
+				clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes1_pll_cmnlc1>;
+				assigned-clock-parents = <&wiz1_pll1_refclk>;
+			};
 		};
 	};
 
@@ -514,8 +570,36 @@
 			#size-cells = <0>;
 			resets = <&serdes_wiz2 0>;
 			reset-names = "sierra_reset";
-			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>;
+			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+			serdes2_refrcv: refrcv {
+				clocks = <&wiz2_pll0_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes2_refrcv1: refrcv1 {
+				clocks = <&wiz2_pll1_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes2_pll_cmnlc: pll_cmnlc {
+				clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes2_pll_cmnlc>;
+				assigned-clock-parents = <&wiz2_pll0_refclk>;
+			};
+
+			serdes2_pll_cmnlc1: pll_cmnlc1 {
+				clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes2_pll_cmnlc1>;
+				assigned-clock-parents = <&wiz2_pll1_refclk>;
+			};
 		};
 	};
 
@@ -571,8 +655,36 @@
 			#size-cells = <0>;
 			resets = <&serdes_wiz3 0>;
 			reset-names = "sierra_reset";
-			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
-			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>;
+			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+			serdes3_refrcv: refrcv {
+				clocks = <&wiz3_pll0_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes3_refrcv1: refrcv1 {
+				clocks = <&wiz3_pll1_refclk>;
+				clock-names = "pll_refclk";
+				#clock-cells = <0>;
+			};
+
+			serdes3_pll_cmnlc: pll_cmnlc {
+				clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes3_pll_cmnlc>;
+				assigned-clock-parents = <&wiz3_pll0_refclk>;
+			};
+
+			serdes3_pll_cmnlc1: pll_cmnlc1 {
+				clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>;
+				clock-names = "pll_refclk", "refrcv";
+				#clock-cells = <0>;
+				assigned-clocks = <&serdes3_pll_cmnlc1>;
+				assigned-clock-parents = <&wiz3_pll1_refclk>;
+			};
 		};
 	};
 
-- 
2.17.1


  parent reply	other threads:[~2020-12-24 11:18 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-24 11:16 [PATCH v3 00/15] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 02/15] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 06/15] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 09/15] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 10/15] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
2020-12-24 11:16 ` Kishon Vijay Abraham I [this message]
2020-12-24 11:16 ` [PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Kishon Vijay Abraham I

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