From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Nishanth Menon <nm@ti.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"
Date: Thu, 24 Dec 2020 16:46:27 +0530 [thread overview]
Message-ID: <20201224111627.32590-16-kishon@ti.com> (raw)
In-Reply-To: <20201224111627.32590-1-kishon@ti.com>
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed in [1].
Re-name subnodes of serdes in J721E to 'phy'.
[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus
Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 788126daf91c..13ae0d89caf2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -358,7 +358,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -685,7 +685,7 @@
};
&serdes0 {
- serdes0_pcie_link: link@0 {
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -695,7 +695,7 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -705,7 +705,7 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
--
2.17.1
prev parent reply other threads:[~2020-12-24 11:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-24 11:16 [PATCH v3 00/15] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 02/15] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 06/15] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 09/15] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 10/15] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` Kishon Vijay Abraham I [this message]
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